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stm32l471xx.h
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1
33#ifndef __STM32L471xx_H
34#define __STM32L471xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
65typedef enum
66{
67/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
68 NonMaskableInt_IRQn = -14,
69 HardFault_IRQn = -13,
70 MemoryManagement_IRQn = -12,
71 BusFault_IRQn = -11,
72 UsageFault_IRQn = -10,
73 SVCall_IRQn = -5,
74 DebugMonitor_IRQn = -4,
75 PendSV_IRQn = -2,
76 SysTick_IRQn = -1,
77/****** STM32 specific Interrupt Numbers **********************************************************************/
78 WWDG_IRQn = 0,
79 PVD_PVM_IRQn = 1,
80 TAMP_STAMP_IRQn = 2,
81 RTC_WKUP_IRQn = 3,
82 FLASH_IRQn = 4,
83 RCC_IRQn = 5,
84 EXTI0_IRQn = 6,
85 EXTI1_IRQn = 7,
86 EXTI2_IRQn = 8,
87 EXTI3_IRQn = 9,
88 EXTI4_IRQn = 10,
89 DMA1_Channel1_IRQn = 11,
90 DMA1_Channel2_IRQn = 12,
91 DMA1_Channel3_IRQn = 13,
92 DMA1_Channel4_IRQn = 14,
93 DMA1_Channel5_IRQn = 15,
94 DMA1_Channel6_IRQn = 16,
95 DMA1_Channel7_IRQn = 17,
96 ADC1_2_IRQn = 18,
97 CAN1_TX_IRQn = 19,
98 CAN1_RX0_IRQn = 20,
99 CAN1_RX1_IRQn = 21,
100 CAN1_SCE_IRQn = 22,
101 EXTI9_5_IRQn = 23,
102 TIM1_BRK_TIM15_IRQn = 24,
103 TIM1_UP_TIM16_IRQn = 25,
104 TIM1_TRG_COM_TIM17_IRQn = 26,
105 TIM1_CC_IRQn = 27,
106 TIM2_IRQn = 28,
107 TIM3_IRQn = 29,
108 TIM4_IRQn = 30,
109 I2C1_EV_IRQn = 31,
110 I2C1_ER_IRQn = 32,
111 I2C2_EV_IRQn = 33,
112 I2C2_ER_IRQn = 34,
113 SPI1_IRQn = 35,
114 SPI2_IRQn = 36,
115 USART1_IRQn = 37,
116 USART2_IRQn = 38,
117 USART3_IRQn = 39,
118 EXTI15_10_IRQn = 40,
119 RTC_Alarm_IRQn = 41,
120 DFSDM1_FLT3_IRQn = 42,
121 TIM8_BRK_IRQn = 43,
122 TIM8_UP_IRQn = 44,
123 TIM8_TRG_COM_IRQn = 45,
124 TIM8_CC_IRQn = 46,
125 ADC3_IRQn = 47,
126 FMC_IRQn = 48,
127 SDMMC1_IRQn = 49,
128 TIM5_IRQn = 50,
129 SPI3_IRQn = 51,
130 UART4_IRQn = 52,
131 UART5_IRQn = 53,
132 TIM6_DAC_IRQn = 54,
133 TIM7_IRQn = 55,
134 DMA2_Channel1_IRQn = 56,
135 DMA2_Channel2_IRQn = 57,
136 DMA2_Channel3_IRQn = 58,
137 DMA2_Channel4_IRQn = 59,
138 DMA2_Channel5_IRQn = 60,
139 DFSDM1_FLT0_IRQn = 61,
140 DFSDM1_FLT1_IRQn = 62,
141 DFSDM1_FLT2_IRQn = 63,
142 COMP_IRQn = 64,
143 LPTIM1_IRQn = 65,
144 LPTIM2_IRQn = 66,
145 DMA2_Channel6_IRQn = 68,
146 DMA2_Channel7_IRQn = 69,
147 LPUART1_IRQn = 70,
148 QUADSPI_IRQn = 71,
149 I2C3_EV_IRQn = 72,
150 I2C3_ER_IRQn = 73,
151 SAI1_IRQn = 74,
152 SAI2_IRQn = 75,
153 SWPMI1_IRQn = 76,
154 TSC_IRQn = 77,
155 RNG_IRQn = 80,
156 FPU_IRQn = 81
157} IRQn_Type;
158
163#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
164#include "system_stm32l4xx.h"
165#include <stdint.h>
166
175typedef struct
176{
177 __IO uint32_t ISR;
178 __IO uint32_t IER;
179 __IO uint32_t CR;
180 __IO uint32_t CFGR;
181 __IO uint32_t CFGR2;
182 __IO uint32_t SMPR1;
183 __IO uint32_t SMPR2;
184 uint32_t RESERVED1;
185 __IO uint32_t TR1;
186 __IO uint32_t TR2;
187 __IO uint32_t TR3;
188 uint32_t RESERVED2;
189 __IO uint32_t SQR1;
190 __IO uint32_t SQR2;
191 __IO uint32_t SQR3;
192 __IO uint32_t SQR4;
193 __IO uint32_t DR;
194 uint32_t RESERVED3;
195 uint32_t RESERVED4;
196 __IO uint32_t JSQR;
197 uint32_t RESERVED5[4];
198 __IO uint32_t OFR1;
199 __IO uint32_t OFR2;
200 __IO uint32_t OFR3;
201 __IO uint32_t OFR4;
202 uint32_t RESERVED6[4];
203 __IO uint32_t JDR1;
204 __IO uint32_t JDR2;
205 __IO uint32_t JDR3;
206 __IO uint32_t JDR4;
207 uint32_t RESERVED7[4];
208 __IO uint32_t AWD2CR;
209 __IO uint32_t AWD3CR;
210 uint32_t RESERVED8;
211 uint32_t RESERVED9;
212 __IO uint32_t DIFSEL;
213 __IO uint32_t CALFACT;
215} ADC_TypeDef;
216
217typedef struct
218{
219 __IO uint32_t CSR;
220 uint32_t RESERVED;
221 __IO uint32_t CCR;
222 __IO uint32_t CDR;
223} ADC_Common_TypeDef;
224
225
230typedef struct
231{
232 __IO uint32_t TIR;
233 __IO uint32_t TDTR;
234 __IO uint32_t TDLR;
235 __IO uint32_t TDHR;
236} CAN_TxMailBox_TypeDef;
237
242typedef struct
243{
244 __IO uint32_t RIR;
245 __IO uint32_t RDTR;
246 __IO uint32_t RDLR;
247 __IO uint32_t RDHR;
248} CAN_FIFOMailBox_TypeDef;
249
254typedef struct
255{
256 __IO uint32_t FR1;
257 __IO uint32_t FR2;
258} CAN_FilterRegister_TypeDef;
259
264typedef struct
265{
266 __IO uint32_t MCR;
267 __IO uint32_t MSR;
268 __IO uint32_t TSR;
269 __IO uint32_t RF0R;
270 __IO uint32_t RF1R;
271 __IO uint32_t IER;
272 __IO uint32_t ESR;
273 __IO uint32_t BTR;
274 uint32_t RESERVED0[88];
275 CAN_TxMailBox_TypeDef sTxMailBox[3];
276 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
277 uint32_t RESERVED1[12];
278 __IO uint32_t FMR;
279 __IO uint32_t FM1R;
280 uint32_t RESERVED2;
281 __IO uint32_t FS1R;
282 uint32_t RESERVED3;
283 __IO uint32_t FFA1R;
284 uint32_t RESERVED4;
285 __IO uint32_t FA1R;
286 uint32_t RESERVED5[8];
287 CAN_FilterRegister_TypeDef sFilterRegister[28];
288} CAN_TypeDef;
289
290
295typedef struct
296{
297 __IO uint32_t CSR;
298} COMP_TypeDef;
299
300typedef struct
301{
302 __IO uint32_t CSR;
303} COMP_Common_TypeDef;
304
309typedef struct
310{
311 __IO uint32_t DR;
312 __IO uint8_t IDR;
313 uint8_t RESERVED0;
314 uint16_t RESERVED1;
315 __IO uint32_t CR;
316 uint32_t RESERVED2;
317 __IO uint32_t INIT;
318 __IO uint32_t POL;
319} CRC_TypeDef;
320
325typedef struct
326{
327 __IO uint32_t CR;
328 __IO uint32_t SWTRIGR;
329 __IO uint32_t DHR12R1;
330 __IO uint32_t DHR12L1;
331 __IO uint32_t DHR8R1;
332 __IO uint32_t DHR12R2;
333 __IO uint32_t DHR12L2;
334 __IO uint32_t DHR8R2;
335 __IO uint32_t DHR12RD;
336 __IO uint32_t DHR12LD;
337 __IO uint32_t DHR8RD;
338 __IO uint32_t DOR1;
339 __IO uint32_t DOR2;
340 __IO uint32_t SR;
341 __IO uint32_t CCR;
342 __IO uint32_t MCR;
343 __IO uint32_t SHSR1;
344 __IO uint32_t SHSR2;
345 __IO uint32_t SHHR;
346 __IO uint32_t SHRR;
347} DAC_TypeDef;
348
352typedef struct
353{
354 __IO uint32_t FLTCR1;
355 __IO uint32_t FLTCR2;
356 __IO uint32_t FLTISR;
357 __IO uint32_t FLTICR;
358 __IO uint32_t FLTJCHGR;
359 __IO uint32_t FLTFCR;
360 __IO uint32_t FLTJDATAR;
361 __IO uint32_t FLTRDATAR;
362 __IO uint32_t FLTAWHTR;
363 __IO uint32_t FLTAWLTR;
364 __IO uint32_t FLTAWSR;
365 __IO uint32_t FLTAWCFR;
366 __IO uint32_t FLTEXMAX;
367 __IO uint32_t FLTEXMIN;
368 __IO uint32_t FLTCNVTIMR;
369} DFSDM_Filter_TypeDef;
370
374typedef struct
375{
376 __IO uint32_t CHCFGR1;
377 __IO uint32_t CHCFGR2;
378 __IO uint32_t CHAWSCDR;
380 __IO uint32_t CHWDATAR;
381 __IO uint32_t CHDATINR;
382} DFSDM_Channel_TypeDef;
383
388typedef struct
389{
390 __IO uint32_t IDCODE;
391 __IO uint32_t CR;
392 __IO uint32_t APB1FZR1;
393 __IO uint32_t APB1FZR2;
394 __IO uint32_t APB2FZ;
395} DBGMCU_TypeDef;
396
397
402typedef struct
403{
404 __IO uint32_t CCR;
405 __IO uint32_t CNDTR;
406 __IO uint32_t CPAR;
407 __IO uint32_t CMAR;
408} DMA_Channel_TypeDef;
409
410typedef struct
411{
412 __IO uint32_t ISR;
413 __IO uint32_t IFCR;
414} DMA_TypeDef;
415
416typedef struct
417{
418 __IO uint32_t CSELR;
419} DMA_Request_TypeDef;
420
421/* Legacy define */
422#define DMA_request_TypeDef DMA_Request_TypeDef
423
424
429typedef struct
430{
431 __IO uint32_t IMR1;
432 __IO uint32_t EMR1;
433 __IO uint32_t RTSR1;
434 __IO uint32_t FTSR1;
435 __IO uint32_t SWIER1;
436 __IO uint32_t PR1;
437 uint32_t RESERVED1;
438 uint32_t RESERVED2;
439 __IO uint32_t IMR2;
440 __IO uint32_t EMR2;
441 __IO uint32_t RTSR2;
442 __IO uint32_t FTSR2;
443 __IO uint32_t SWIER2;
444 __IO uint32_t PR2;
445} EXTI_TypeDef;
446
447
452typedef struct
453{
454 __IO uint32_t CSSA;
455 __IO uint32_t CSL;
456 __IO uint32_t NVDSSA;
457 __IO uint32_t NVDSL;
458 __IO uint32_t VDSSA ;
459 __IO uint32_t VDSL ;
460 uint32_t RESERVED1;
461 uint32_t RESERVED2;
462 __IO uint32_t CR ;
463} FIREWALL_TypeDef;
464
465
470typedef struct
471{
472 __IO uint32_t ACR;
473 __IO uint32_t PDKEYR;
474 __IO uint32_t KEYR;
475 __IO uint32_t OPTKEYR;
476 __IO uint32_t SR;
477 __IO uint32_t CR;
478 __IO uint32_t ECCR;
479 __IO uint32_t RESERVED1;
480 __IO uint32_t OPTR;
481 __IO uint32_t PCROP1SR;
482 __IO uint32_t PCROP1ER;
483 __IO uint32_t WRP1AR;
484 __IO uint32_t WRP1BR;
485 uint32_t RESERVED2[4];
486 __IO uint32_t PCROP2SR;
487 __IO uint32_t PCROP2ER;
488 __IO uint32_t WRP2AR;
489 __IO uint32_t WRP2BR;
490} FLASH_TypeDef;
491
492
497typedef struct
498{
499 __IO uint32_t BTCR[8];
500} FMC_Bank1_TypeDef;
501
506typedef struct
507{
508 __IO uint32_t BWTR[7];
509} FMC_Bank1E_TypeDef;
510
515typedef struct
516{
517 __IO uint32_t PCR;
518 __IO uint32_t SR;
519 __IO uint32_t PMEM;
520 __IO uint32_t PATT;
521 uint32_t RESERVED0;
522 __IO uint32_t ECCR;
523} FMC_Bank3_TypeDef;
524
529typedef struct
530{
531 __IO uint32_t MODER;
532 __IO uint32_t OTYPER;
533 __IO uint32_t OSPEEDR;
534 __IO uint32_t PUPDR;
535 __IO uint32_t IDR;
536 __IO uint32_t ODR;
537 __IO uint32_t BSRR;
538 __IO uint32_t LCKR;
539 __IO uint32_t AFR[2];
540 __IO uint32_t BRR;
541 __IO uint32_t ASCR;
543} GPIO_TypeDef;
544
545
550typedef struct
551{
552 __IO uint32_t CR1;
553 __IO uint32_t CR2;
554 __IO uint32_t OAR1;
555 __IO uint32_t OAR2;
556 __IO uint32_t TIMINGR;
557 __IO uint32_t TIMEOUTR;
558 __IO uint32_t ISR;
559 __IO uint32_t ICR;
560 __IO uint32_t PECR;
561 __IO uint32_t RXDR;
562 __IO uint32_t TXDR;
563} I2C_TypeDef;
564
569typedef struct
570{
571 __IO uint32_t KR;
572 __IO uint32_t PR;
573 __IO uint32_t RLR;
574 __IO uint32_t SR;
575 __IO uint32_t WINR;
576} IWDG_TypeDef;
577
581typedef struct
582{
583 __IO uint32_t ISR;
584 __IO uint32_t ICR;
585 __IO uint32_t IER;
586 __IO uint32_t CFGR;
587 __IO uint32_t CR;
588 __IO uint32_t CMP;
589 __IO uint32_t ARR;
590 __IO uint32_t CNT;
591 __IO uint32_t OR;
592} LPTIM_TypeDef;
593
598typedef struct
599{
600 __IO uint32_t CSR;
601 __IO uint32_t OTR;
602 __IO uint32_t LPOTR;
603} OPAMP_TypeDef;
604
605typedef struct
606{
607 __IO uint32_t CSR;
608} OPAMP_Common_TypeDef;
609
614typedef struct
615{
616 __IO uint32_t CR1;
617 __IO uint32_t CR2;
618 __IO uint32_t CR3;
619 __IO uint32_t CR4;
620 __IO uint32_t SR1;
621 __IO uint32_t SR2;
622 __IO uint32_t SCR;
623 uint32_t RESERVED;
624 __IO uint32_t PUCRA;
625 __IO uint32_t PDCRA;
626 __IO uint32_t PUCRB;
627 __IO uint32_t PDCRB;
628 __IO uint32_t PUCRC;
629 __IO uint32_t PDCRC;
630 __IO uint32_t PUCRD;
631 __IO uint32_t PDCRD;
632 __IO uint32_t PUCRE;
633 __IO uint32_t PDCRE;
634 __IO uint32_t PUCRF;
635 __IO uint32_t PDCRF;
636 __IO uint32_t PUCRG;
637 __IO uint32_t PDCRG;
638 __IO uint32_t PUCRH;
639 __IO uint32_t PDCRH;
640} PWR_TypeDef;
641
642
647typedef struct
648{
649 __IO uint32_t CR;
650 __IO uint32_t DCR;
651 __IO uint32_t SR;
652 __IO uint32_t FCR;
653 __IO uint32_t DLR;
654 __IO uint32_t CCR;
655 __IO uint32_t AR;
656 __IO uint32_t ABR;
657 __IO uint32_t DR;
658 __IO uint32_t PSMKR;
659 __IO uint32_t PSMAR;
660 __IO uint32_t PIR;
661 __IO uint32_t LPTR;
662} QUADSPI_TypeDef;
663
664
669typedef struct
670{
671 __IO uint32_t CR;
672 __IO uint32_t ICSCR;
673 __IO uint32_t CFGR;
674 __IO uint32_t PLLCFGR;
675 __IO uint32_t PLLSAI1CFGR;
676 __IO uint32_t PLLSAI2CFGR;
677 __IO uint32_t CIER;
678 __IO uint32_t CIFR;
679 __IO uint32_t CICR;
680 uint32_t RESERVED0;
681 __IO uint32_t AHB1RSTR;
682 __IO uint32_t AHB2RSTR;
683 __IO uint32_t AHB3RSTR;
684 uint32_t RESERVED1;
685 __IO uint32_t APB1RSTR1;
686 __IO uint32_t APB1RSTR2;
687 __IO uint32_t APB2RSTR;
688 uint32_t RESERVED2;
689 __IO uint32_t AHB1ENR;
690 __IO uint32_t AHB2ENR;
691 __IO uint32_t AHB3ENR;
692 uint32_t RESERVED3;
693 __IO uint32_t APB1ENR1;
694 __IO uint32_t APB1ENR2;
695 __IO uint32_t APB2ENR;
696 uint32_t RESERVED4;
697 __IO uint32_t AHB1SMENR;
698 __IO uint32_t AHB2SMENR;
699 __IO uint32_t AHB3SMENR;
700 uint32_t RESERVED5;
701 __IO uint32_t APB1SMENR1;
702 __IO uint32_t APB1SMENR2;
703 __IO uint32_t APB2SMENR;
704 uint32_t RESERVED6;
705 __IO uint32_t CCIPR;
706 uint32_t RESERVED7;
707 __IO uint32_t BDCR;
708 __IO uint32_t CSR;
709} RCC_TypeDef;
710
715typedef struct
716{
717 __IO uint32_t TR;
718 __IO uint32_t DR;
719 __IO uint32_t CR;
720 __IO uint32_t ISR;
721 __IO uint32_t PRER;
722 __IO uint32_t WUTR;
723 uint32_t reserved;
724 __IO uint32_t ALRMAR;
725 __IO uint32_t ALRMBR;
726 __IO uint32_t WPR;
727 __IO uint32_t SSR;
728 __IO uint32_t SHIFTR;
729 __IO uint32_t TSTR;
730 __IO uint32_t TSDR;
731 __IO uint32_t TSSSR;
732 __IO uint32_t CALR;
733 __IO uint32_t TAMPCR;
734 __IO uint32_t ALRMASSR;
735 __IO uint32_t ALRMBSSR;
736 __IO uint32_t OR;
737 __IO uint32_t BKP0R;
738 __IO uint32_t BKP1R;
739 __IO uint32_t BKP2R;
740 __IO uint32_t BKP3R;
741 __IO uint32_t BKP4R;
742 __IO uint32_t BKP5R;
743 __IO uint32_t BKP6R;
744 __IO uint32_t BKP7R;
745 __IO uint32_t BKP8R;
746 __IO uint32_t BKP9R;
747 __IO uint32_t BKP10R;
748 __IO uint32_t BKP11R;
749 __IO uint32_t BKP12R;
750 __IO uint32_t BKP13R;
751 __IO uint32_t BKP14R;
752 __IO uint32_t BKP15R;
753 __IO uint32_t BKP16R;
754 __IO uint32_t BKP17R;
755 __IO uint32_t BKP18R;
756 __IO uint32_t BKP19R;
757 __IO uint32_t BKP20R;
758 __IO uint32_t BKP21R;
759 __IO uint32_t BKP22R;
760 __IO uint32_t BKP23R;
761 __IO uint32_t BKP24R;
762 __IO uint32_t BKP25R;
763 __IO uint32_t BKP26R;
764 __IO uint32_t BKP27R;
765 __IO uint32_t BKP28R;
766 __IO uint32_t BKP29R;
767 __IO uint32_t BKP30R;
768 __IO uint32_t BKP31R;
769} RTC_TypeDef;
770
775typedef struct
776{
777 __IO uint32_t GCR;
778} SAI_TypeDef;
779
780typedef struct
781{
782 __IO uint32_t CR1;
783 __IO uint32_t CR2;
784 __IO uint32_t FRCR;
785 __IO uint32_t SLOTR;
786 __IO uint32_t IMR;
787 __IO uint32_t SR;
788 __IO uint32_t CLRFR;
789 __IO uint32_t DR;
790} SAI_Block_TypeDef;
791
792
797typedef struct
798{
799 __IO uint32_t POWER;
800 __IO uint32_t CLKCR;
801 __IO uint32_t ARG;
802 __IO uint32_t CMD;
803 __I uint32_t RESPCMD;
804 __I uint32_t RESP1;
805 __I uint32_t RESP2;
806 __I uint32_t RESP3;
807 __I uint32_t RESP4;
808 __IO uint32_t DTIMER;
809 __IO uint32_t DLEN;
810 __IO uint32_t DCTRL;
811 __I uint32_t DCOUNT;
812 __I uint32_t STA;
813 __IO uint32_t ICR;
814 __IO uint32_t MASK;
815 uint32_t RESERVED0[2];
816 __I uint32_t FIFOCNT;
817 uint32_t RESERVED1[13];
818 __IO uint32_t FIFO;
819} SDMMC_TypeDef;
820
821
826typedef struct
827{
828 __IO uint32_t CR1;
829 __IO uint32_t CR2;
830 __IO uint32_t SR;
831 __IO uint32_t DR;
832 __IO uint32_t CRCPR;
833 __IO uint32_t RXCRCR;
834 __IO uint32_t TXCRCR;
835} SPI_TypeDef;
836
837
842typedef struct
843{
844 __IO uint32_t CR;
845 __IO uint32_t BRR;
846 uint32_t RESERVED1;
847 __IO uint32_t ISR;
848 __IO uint32_t ICR;
849 __IO uint32_t IER;
850 __IO uint32_t RFL;
851 __IO uint32_t TDR;
852 __IO uint32_t RDR;
853 __IO uint32_t OR;
854} SWPMI_TypeDef;
855
856
861typedef struct
862{
863 __IO uint32_t MEMRMP;
864 __IO uint32_t CFGR1;
865 __IO uint32_t EXTICR[4];
866 __IO uint32_t SCSR;
867 __IO uint32_t CFGR2;
868 __IO uint32_t SWPR;
869 __IO uint32_t SKR;
870} SYSCFG_TypeDef;
871
872
877typedef struct
878{
879 __IO uint32_t CR1;
880 __IO uint32_t CR2;
881 __IO uint32_t SMCR;
882 __IO uint32_t DIER;
883 __IO uint32_t SR;
884 __IO uint32_t EGR;
885 __IO uint32_t CCMR1;
886 __IO uint32_t CCMR2;
887 __IO uint32_t CCER;
888 __IO uint32_t CNT;
889 __IO uint32_t PSC;
890 __IO uint32_t ARR;
891 __IO uint32_t RCR;
892 __IO uint32_t CCR1;
893 __IO uint32_t CCR2;
894 __IO uint32_t CCR3;
895 __IO uint32_t CCR4;
896 __IO uint32_t BDTR;
897 __IO uint32_t DCR;
898 __IO uint32_t DMAR;
899 __IO uint32_t OR1;
900 __IO uint32_t CCMR3;
901 __IO uint32_t CCR5;
902 __IO uint32_t CCR6;
903 __IO uint32_t OR2;
904 __IO uint32_t OR3;
905} TIM_TypeDef;
906
907
912typedef struct
913{
914 __IO uint32_t CR;
915 __IO uint32_t IER;
916 __IO uint32_t ICR;
917 __IO uint32_t ISR;
918 __IO uint32_t IOHCR;
919 uint32_t RESERVED1;
920 __IO uint32_t IOASCR;
921 uint32_t RESERVED2;
922 __IO uint32_t IOSCR;
923 uint32_t RESERVED3;
924 __IO uint32_t IOCCR;
925 uint32_t RESERVED4;
926 __IO uint32_t IOGCSR;
927 __IO uint32_t IOGXCR[8];
928} TSC_TypeDef;
929
934typedef struct
935{
936 __IO uint32_t CR1;
937 __IO uint32_t CR2;
938 __IO uint32_t CR3;
939 __IO uint32_t BRR;
940 __IO uint16_t GTPR;
941 uint16_t RESERVED2;
942 __IO uint32_t RTOR;
943 __IO uint16_t RQR;
944 uint16_t RESERVED3;
945 __IO uint32_t ISR;
946 __IO uint32_t ICR;
947 __IO uint16_t RDR;
948 uint16_t RESERVED4;
949 __IO uint16_t TDR;
950 uint16_t RESERVED5;
951} USART_TypeDef;
952
957typedef struct
958{
959 __IO uint32_t CSR;
960 __IO uint32_t CCR;
961} VREFBUF_TypeDef;
962
967typedef struct
968{
969 __IO uint32_t CR;
970 __IO uint32_t CFR;
971 __IO uint32_t SR;
972} WWDG_TypeDef;
973
978typedef struct
979{
980 __IO uint32_t CR;
981 __IO uint32_t SR;
982 __IO uint32_t DR;
983} RNG_TypeDef;
984
992#define FLASH_BASE (0x08000000UL)
993#define FLASH_END (0x080FFFFFUL)
994#define FLASH_BANK1_END (0x0807FFFFUL)
995#define FLASH_BANK2_END (0x080FFFFFUL)
996#define SRAM1_BASE (0x20000000UL)
997#define SRAM2_BASE (0x10000000UL)
998#define PERIPH_BASE (0x40000000UL)
999#define FMC_BASE (0x60000000UL)
1000#define QSPI_BASE (0x90000000UL)
1002#define FMC_R_BASE (0xA0000000UL)
1003#define QSPI_R_BASE (0xA0001000UL)
1004#define SRAM1_BB_BASE (0x22000000UL)
1005#define PERIPH_BB_BASE (0x42000000UL)
1007/* Legacy defines */
1008#define SRAM_BASE SRAM1_BASE
1009#define SRAM_BB_BASE SRAM1_BB_BASE
1010
1011#define SRAM1_SIZE_MAX (0x00018000UL)
1012#define SRAM2_SIZE (0x00008000UL)
1014#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFF75E0)
1015
1016#define FLASH_SIZE (((((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU))== 0x0000FFFFU)) ? (0x400U << 10U) : \
1017 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0000FFFFU)) << 10U))
1018
1020#define APB1PERIPH_BASE PERIPH_BASE
1021#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1022#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1023#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
1024
1025#define FMC_BANK1 FMC_BASE
1026#define FMC_BANK1_1 FMC_BANK1
1027#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
1028#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
1029#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
1030#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
1031
1033#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1034#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1035#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1036#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1037#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1038#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1039#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1040#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1041#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1042#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1043#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1044#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1045#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1046#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1047#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1048#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1049#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1050#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1051#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1052#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1053#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1054#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
1055#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
1056#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL)
1057#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810UL)
1058#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
1059#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
1060#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL)
1061#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
1062
1063
1065#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
1066#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
1067#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
1068#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
1069#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
1070#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL)
1071#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL)
1072#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
1073#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1074#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
1075#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
1076#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
1077#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
1078#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
1079#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
1080#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
1081#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
1082#define SAI2_BASE (APB2PERIPH_BASE + 0x5800UL)
1083#define SAI2_Block_A_BASE (SAI2_BASE + 0x0004UL)
1084#define SAI2_Block_B_BASE (SAI2_BASE + 0x0024UL)
1085#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000UL)
1086#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x0000UL)
1087#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x0020UL)
1088#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x0040UL)
1089#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x0060UL)
1090#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x0080UL)
1091#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0x00A0UL)
1092#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0x00C0UL)
1093#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0x00E0UL)
1094#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x0100UL)
1095#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x0180UL)
1096#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x0200UL)
1097#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x0280UL)
1098
1100#define DMA1_BASE (AHB1PERIPH_BASE)
1101#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
1102#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
1103#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
1104#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1105#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL)
1106
1107
1108#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
1109#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
1110#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
1111#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
1112#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
1113#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
1114#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
1115#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
1116
1117
1118#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
1119#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
1120#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
1121#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
1122#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
1123#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
1124#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
1125#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
1126
1127
1129#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
1130#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
1131#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
1132#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
1133#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
1134#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
1135#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
1136#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL)
1137
1138
1139#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
1140#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100UL)
1141#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200UL)
1142#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
1143
1144
1145#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
1146
1147
1149#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1150#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1151#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1152
1153/* Debug MCU registers base address */
1154#define DBGMCU_BASE (0xE0042000UL)
1155
1156
1157#define PACKAGE_BASE (0x1FFF7500UL)
1158#define UID_BASE (0x1FFF7590UL)
1159#define FLASHSIZE_BASE (0x1FFF75E0UL)
1167#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1168#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1169#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1170#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1171#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1172#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1173#define RTC ((RTC_TypeDef *) RTC_BASE)
1174#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1175#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1176#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1177#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1178#define USART2 ((USART_TypeDef *) USART2_BASE)
1179#define USART3 ((USART_TypeDef *) USART3_BASE)
1180#define UART4 ((USART_TypeDef *) UART4_BASE)
1181#define UART5 ((USART_TypeDef *) UART5_BASE)
1182#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1183#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1184#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1185#define CAN ((CAN_TypeDef *) CAN1_BASE)
1186#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1187#define PWR ((PWR_TypeDef *) PWR_BASE)
1188#define DAC ((DAC_TypeDef *) DAC1_BASE)
1189#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
1190#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
1191#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
1192#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
1193#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1194#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1195#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
1196#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
1197#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
1198
1199#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1200#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
1201#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
1202#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
1203#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
1204#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1205#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
1206#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1207#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1208#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1209#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1210#define USART1 ((USART_TypeDef *) USART1_BASE)
1211#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
1212#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
1213#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
1214#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1215#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1216#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1217#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1218#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1219#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1220#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1221#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1222#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1223#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1224#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1225#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1226#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1227#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1228#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1229#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1230#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1231#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1232/* Aliases to keep compatibility after DFSDM renaming */
1233#define DFSDM_Channel0 DFSDM1_Channel0
1234#define DFSDM_Channel1 DFSDM1_Channel1
1235#define DFSDM_Channel2 DFSDM1_Channel2
1236#define DFSDM_Channel3 DFSDM1_Channel3
1237#define DFSDM_Channel4 DFSDM1_Channel4
1238#define DFSDM_Channel5 DFSDM1_Channel5
1239#define DFSDM_Channel6 DFSDM1_Channel6
1240#define DFSDM_Channel7 DFSDM1_Channel7
1241#define DFSDM_Filter0 DFSDM1_Filter0
1242#define DFSDM_Filter1 DFSDM1_Filter1
1243#define DFSDM_Filter2 DFSDM1_Filter2
1244#define DFSDM_Filter3 DFSDM1_Filter3
1245#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1246#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1247#define RCC ((RCC_TypeDef *) RCC_BASE)
1248#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1249#define CRC ((CRC_TypeDef *) CRC_BASE)
1250#define TSC ((TSC_TypeDef *) TSC_BASE)
1251
1252#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1253#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1254#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1255#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1256#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1257#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1258#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1259#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1260#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1261#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1262#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1263#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1264#define RNG ((RNG_TypeDef *) RNG_BASE)
1265
1266
1267#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1268#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1269#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1270#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1271#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1272#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1273#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1274#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1275
1276
1277#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1278#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1279#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1280#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1281#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1282#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1283#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1284#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1285
1286
1287#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1288#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1289#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1290
1291#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1292
1293#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1294
1306#define LSI_STARTUP_TIME 130U
1316/******************************************************************************/
1317/* Peripheral Registers_Bits_Definition */
1318/******************************************************************************/
1319
1320/******************************************************************************/
1321/* */
1322/* Analog to Digital Converter */
1323/* */
1324/******************************************************************************/
1325
1326/*
1327 * @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
1328 */
1329#define ADC_MULTIMODE_SUPPORT
1331/******************** Bit definition for ADC_ISR register *******************/
1332#define ADC_ISR_ADRDY_Pos (0U)
1333#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
1334#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
1335#define ADC_ISR_EOSMP_Pos (1U)
1336#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
1337#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
1338#define ADC_ISR_EOC_Pos (2U)
1339#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
1340#define ADC_ISR_EOC ADC_ISR_EOC_Msk
1341#define ADC_ISR_EOS_Pos (3U)
1342#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
1343#define ADC_ISR_EOS ADC_ISR_EOS_Msk
1344#define ADC_ISR_OVR_Pos (4U)
1345#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
1346#define ADC_ISR_OVR ADC_ISR_OVR_Msk
1347#define ADC_ISR_JEOC_Pos (5U)
1348#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
1349#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
1350#define ADC_ISR_JEOS_Pos (6U)
1351#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
1352#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
1353#define ADC_ISR_AWD1_Pos (7U)
1354#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
1355#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
1356#define ADC_ISR_AWD2_Pos (8U)
1357#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
1358#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
1359#define ADC_ISR_AWD3_Pos (9U)
1360#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
1361#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
1362#define ADC_ISR_JQOVF_Pos (10U)
1363#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
1364#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
1366/******************** Bit definition for ADC_IER register *******************/
1367#define ADC_IER_ADRDYIE_Pos (0U)
1368#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
1369#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
1370#define ADC_IER_EOSMPIE_Pos (1U)
1371#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
1372#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
1373#define ADC_IER_EOCIE_Pos (2U)
1374#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
1375#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
1376#define ADC_IER_EOSIE_Pos (3U)
1377#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
1378#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
1379#define ADC_IER_OVRIE_Pos (4U)
1380#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
1381#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
1382#define ADC_IER_JEOCIE_Pos (5U)
1383#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
1384#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
1385#define ADC_IER_JEOSIE_Pos (6U)
1386#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
1387#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
1388#define ADC_IER_AWD1IE_Pos (7U)
1389#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
1390#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
1391#define ADC_IER_AWD2IE_Pos (8U)
1392#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
1393#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
1394#define ADC_IER_AWD3IE_Pos (9U)
1395#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
1396#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
1397#define ADC_IER_JQOVFIE_Pos (10U)
1398#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
1399#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
1401/* Legacy defines */
1402#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
1403#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
1404#define ADC_IER_EOC (ADC_IER_EOCIE)
1405#define ADC_IER_EOS (ADC_IER_EOSIE)
1406#define ADC_IER_OVR (ADC_IER_OVRIE)
1407#define ADC_IER_JEOC (ADC_IER_JEOCIE)
1408#define ADC_IER_JEOS (ADC_IER_JEOSIE)
1409#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
1410#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
1411#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
1412#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
1413
1414/******************** Bit definition for ADC_CR register ********************/
1415#define ADC_CR_ADEN_Pos (0U)
1416#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
1417#define ADC_CR_ADEN ADC_CR_ADEN_Msk
1418#define ADC_CR_ADDIS_Pos (1U)
1419#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
1420#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
1421#define ADC_CR_ADSTART_Pos (2U)
1422#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
1423#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
1424#define ADC_CR_JADSTART_Pos (3U)
1425#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
1426#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
1427#define ADC_CR_ADSTP_Pos (4U)
1428#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
1429#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
1430#define ADC_CR_JADSTP_Pos (5U)
1431#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
1432#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
1433#define ADC_CR_ADVREGEN_Pos (28U)
1434#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
1435#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
1436#define ADC_CR_DEEPPWD_Pos (29U)
1437#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
1438#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
1439#define ADC_CR_ADCALDIF_Pos (30U)
1440#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
1441#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
1442#define ADC_CR_ADCAL_Pos (31U)
1443#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
1444#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
1446/******************** Bit definition for ADC_CFGR register ******************/
1447#define ADC_CFGR_DMAEN_Pos (0U)
1448#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)
1449#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk
1450#define ADC_CFGR_DMACFG_Pos (1U)
1451#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)
1452#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk
1454#define ADC_CFGR_RES_Pos (3U)
1455#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)
1456#define ADC_CFGR_RES ADC_CFGR_RES_Msk
1457#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
1458#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
1460#define ADC_CFGR_ALIGN_Pos (5U)
1461#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)
1462#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk
1464#define ADC_CFGR_EXTSEL_Pos (6U)
1465#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos)
1466#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
1467#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)
1468#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)
1469#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)
1470#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)
1472#define ADC_CFGR_EXTEN_Pos (10U)
1473#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
1474#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
1475#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
1476#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
1478#define ADC_CFGR_OVRMOD_Pos (12U)
1479#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
1480#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
1481#define ADC_CFGR_CONT_Pos (13U)
1482#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
1483#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
1484#define ADC_CFGR_AUTDLY_Pos (14U)
1485#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
1486#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
1488#define ADC_CFGR_DISCEN_Pos (16U)
1489#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
1490#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
1492#define ADC_CFGR_DISCNUM_Pos (17U)
1493#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
1494#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
1495#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
1496#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
1497#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
1499#define ADC_CFGR_JDISCEN_Pos (20U)
1500#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
1501#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
1502#define ADC_CFGR_JQM_Pos (21U)
1503#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
1504#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
1505#define ADC_CFGR_AWD1SGL_Pos (22U)
1506#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
1507#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
1508#define ADC_CFGR_AWD1EN_Pos (23U)
1509#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
1510#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
1511#define ADC_CFGR_JAWD1EN_Pos (24U)
1512#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
1513#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
1514#define ADC_CFGR_JAUTO_Pos (25U)
1515#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
1516#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
1518#define ADC_CFGR_AWD1CH_Pos (26U)
1519#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
1520#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
1521#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
1522#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
1523#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
1524#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
1525#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
1527#define ADC_CFGR_JQDIS_Pos (31U)
1528#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
1529#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
1531/******************** Bit definition for ADC_CFGR2 register *****************/
1532#define ADC_CFGR2_ROVSE_Pos (0U)
1533#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
1534#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
1535#define ADC_CFGR2_JOVSE_Pos (1U)
1536#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
1537#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
1539#define ADC_CFGR2_OVSR_Pos (2U)
1540#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)
1541#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
1542#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)
1543#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)
1544#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)
1546#define ADC_CFGR2_OVSS_Pos (5U)
1547#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
1548#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
1549#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
1550#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
1551#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
1552#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
1554#define ADC_CFGR2_TROVS_Pos (9U)
1555#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
1556#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
1557#define ADC_CFGR2_ROVSM_Pos (10U)
1558#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
1559#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
1561/******************** Bit definition for ADC_SMPR1 register *****************/
1562#define ADC_SMPR1_SMP0_Pos (0U)
1563#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
1564#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
1565#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
1566#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
1567#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
1569#define ADC_SMPR1_SMP1_Pos (3U)
1570#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
1571#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
1572#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
1573#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
1574#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
1576#define ADC_SMPR1_SMP2_Pos (6U)
1577#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
1578#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
1579#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
1580#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
1581#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
1583#define ADC_SMPR1_SMP3_Pos (9U)
1584#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
1585#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
1586#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
1587#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
1588#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
1590#define ADC_SMPR1_SMP4_Pos (12U)
1591#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
1592#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
1593#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
1594#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
1595#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
1597#define ADC_SMPR1_SMP5_Pos (15U)
1598#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
1599#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
1600#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
1601#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
1602#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
1604#define ADC_SMPR1_SMP6_Pos (18U)
1605#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
1606#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
1607#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
1608#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
1609#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
1611#define ADC_SMPR1_SMP7_Pos (21U)
1612#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
1613#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
1614#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
1615#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
1616#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
1618#define ADC_SMPR1_SMP8_Pos (24U)
1619#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
1620#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
1621#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
1622#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
1623#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
1625#define ADC_SMPR1_SMP9_Pos (27U)
1626#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
1627#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
1628#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
1629#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
1630#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
1632/******************** Bit definition for ADC_SMPR2 register *****************/
1633#define ADC_SMPR2_SMP10_Pos (0U)
1634#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
1635#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
1636#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
1637#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
1638#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
1640#define ADC_SMPR2_SMP11_Pos (3U)
1641#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
1642#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
1643#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
1644#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
1645#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
1647#define ADC_SMPR2_SMP12_Pos (6U)
1648#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
1649#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
1650#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
1651#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
1652#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
1654#define ADC_SMPR2_SMP13_Pos (9U)
1655#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
1656#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
1657#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
1658#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
1659#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
1661#define ADC_SMPR2_SMP14_Pos (12U)
1662#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
1663#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
1664#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
1665#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
1666#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
1668#define ADC_SMPR2_SMP15_Pos (15U)
1669#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
1670#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
1671#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
1672#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
1673#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
1675#define ADC_SMPR2_SMP16_Pos (18U)
1676#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
1677#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
1678#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
1679#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
1680#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
1682#define ADC_SMPR2_SMP17_Pos (21U)
1683#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
1684#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
1685#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
1686#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
1687#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
1689#define ADC_SMPR2_SMP18_Pos (24U)
1690#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
1691#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
1692#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
1693#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
1694#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
1696/******************** Bit definition for ADC_TR1 register *******************/
1697#define ADC_TR1_LT1_Pos (0U)
1698#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)
1699#define ADC_TR1_LT1 ADC_TR1_LT1_Msk
1700#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos)
1701#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos)
1702#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos)
1703#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos)
1704#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos)
1705#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos)
1706#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos)
1707#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos)
1708#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos)
1709#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos)
1710#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos)
1711#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos)
1713#define ADC_TR1_HT1_Pos (16U)
1714#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)
1715#define ADC_TR1_HT1 ADC_TR1_HT1_Msk
1716#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos)
1717#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos)
1718#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos)
1719#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos)
1720#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos)
1721#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos)
1722#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos)
1723#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos)
1724#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos)
1725#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos)
1726#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos)
1727#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos)
1729/******************** Bit definition for ADC_TR2 register *******************/
1730#define ADC_TR2_LT2_Pos (0U)
1731#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)
1732#define ADC_TR2_LT2 ADC_TR2_LT2_Msk
1733#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos)
1734#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos)
1735#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos)
1736#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos)
1737#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos)
1738#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos)
1739#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos)
1740#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos)
1742#define ADC_TR2_HT2_Pos (16U)
1743#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)
1744#define ADC_TR2_HT2 ADC_TR2_HT2_Msk
1745#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos)
1746#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos)
1747#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos)
1748#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos)
1749#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos)
1750#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos)
1751#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos)
1752#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos)
1754/******************** Bit definition for ADC_TR3 register *******************/
1755#define ADC_TR3_LT3_Pos (0U)
1756#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)
1757#define ADC_TR3_LT3 ADC_TR3_LT3_Msk
1758#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos)
1759#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos)
1760#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos)
1761#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos)
1762#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos)
1763#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos)
1764#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos)
1765#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos)
1767#define ADC_TR3_HT3_Pos (16U)
1768#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)
1769#define ADC_TR3_HT3 ADC_TR3_HT3_Msk
1770#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos)
1771#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos)
1772#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos)
1773#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos)
1774#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos)
1775#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos)
1776#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos)
1777#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos)
1779/******************** Bit definition for ADC_SQR1 register ******************/
1780#define ADC_SQR1_L_Pos (0U)
1781#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1782#define ADC_SQR1_L ADC_SQR1_L_Msk
1783#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1784#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1785#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1786#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1788#define ADC_SQR1_SQ1_Pos (6U)
1789#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
1790#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
1791#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
1792#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
1793#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
1794#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
1795#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
1797#define ADC_SQR1_SQ2_Pos (12U)
1798#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
1799#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
1800#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
1801#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
1802#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
1803#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
1804#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
1806#define ADC_SQR1_SQ3_Pos (18U)
1807#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
1808#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
1809#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
1810#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
1811#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
1812#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
1813#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
1815#define ADC_SQR1_SQ4_Pos (24U)
1816#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
1817#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
1818#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
1819#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
1820#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
1821#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
1822#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
1824/******************** Bit definition for ADC_SQR2 register ******************/
1825#define ADC_SQR2_SQ5_Pos (0U)
1826#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
1827#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
1828#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
1829#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
1830#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
1831#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
1832#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
1834#define ADC_SQR2_SQ6_Pos (6U)
1835#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
1836#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
1837#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
1838#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
1839#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
1840#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
1841#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
1843#define ADC_SQR2_SQ7_Pos (12U)
1844#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1845#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1846#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1847#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1848#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1849#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1850#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1852#define ADC_SQR2_SQ8_Pos (18U)
1853#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1854#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1855#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1856#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1857#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1858#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1859#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1861#define ADC_SQR2_SQ9_Pos (24U)
1862#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1863#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1864#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1865#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1866#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1867#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1868#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1870/******************** Bit definition for ADC_SQR3 register ******************/
1871#define ADC_SQR3_SQ10_Pos (0U)
1872#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
1873#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
1874#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
1875#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
1876#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
1877#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
1878#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
1880#define ADC_SQR3_SQ11_Pos (6U)
1881#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
1882#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
1883#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
1884#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
1885#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
1886#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
1887#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
1889#define ADC_SQR3_SQ12_Pos (12U)
1890#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
1891#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
1892#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
1893#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
1894#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
1895#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
1896#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
1898#define ADC_SQR3_SQ13_Pos (18U)
1899#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
1900#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
1901#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
1902#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
1903#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
1904#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
1905#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
1907#define ADC_SQR3_SQ14_Pos (24U)
1908#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
1909#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
1910#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
1911#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
1912#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
1913#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
1914#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
1916/******************** Bit definition for ADC_SQR4 register ******************/
1917#define ADC_SQR4_SQ15_Pos (0U)
1918#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
1919#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
1920#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
1921#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
1922#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
1923#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
1924#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
1926#define ADC_SQR4_SQ16_Pos (6U)
1927#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
1928#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
1929#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
1930#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
1931#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
1932#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
1933#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
1935/******************** Bit definition for ADC_DR register ********************/
1936#define ADC_DR_RDATA_Pos (0U)
1937#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)
1938#define ADC_DR_RDATA ADC_DR_RDATA_Msk
1939#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos)
1940#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos)
1941#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos)
1942#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos)
1943#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos)
1944#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos)
1945#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos)
1946#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos)
1947#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos)
1948#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos)
1949#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos)
1950#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos)
1951#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos)
1952#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos)
1953#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos)
1954#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos)
1956/******************** Bit definition for ADC_JSQR register ******************/
1957#define ADC_JSQR_JL_Pos (0U)
1958#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1959#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1960#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1961#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1963#define ADC_JSQR_JEXTSEL_Pos (2U)
1964#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos)
1965#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
1966#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)
1967#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)
1968#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)
1969#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)
1971#define ADC_JSQR_JEXTEN_Pos (6U)
1972#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
1973#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
1974#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
1975#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
1977#define ADC_JSQR_JSQ1_Pos (8U)
1978#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1979#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1980#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1981#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1982#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1983#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1984#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1986#define ADC_JSQR_JSQ2_Pos (14U)
1987#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1988#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1989#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1990#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1991#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1992#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1993#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1995#define ADC_JSQR_JSQ3_Pos (20U)
1996#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1997#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1998#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1999#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
2000#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
2001#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
2002#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
2004#define ADC_JSQR_JSQ4_Pos (26U)
2005#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
2006#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
2007#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
2008#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
2009#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
2010#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
2011#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
2013/******************** Bit definition for ADC_OFR1 register ******************/
2014#define ADC_OFR1_OFFSET1_Pos (0U)
2015#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)
2016#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
2017#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos)
2018#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos)
2019#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos)
2020#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos)
2021#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos)
2022#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos)
2023#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos)
2024#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos)
2025#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos)
2026#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos)
2027#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos)
2028#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos)
2030#define ADC_OFR1_OFFSET1_CH_Pos (26U)
2031#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
2032#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
2033#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
2034#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
2035#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
2036#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
2037#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
2039#define ADC_OFR1_OFFSET1_EN_Pos (31U)
2040#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)
2041#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk
2043/******************** Bit definition for ADC_OFR2 register ******************/
2044#define ADC_OFR2_OFFSET2_Pos (0U)
2045#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)
2046#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
2047#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos)
2048#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos)
2049#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos)
2050#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos)
2051#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos)
2052#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos)
2053#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos)
2054#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos)
2055#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos)
2056#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos)
2057#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos)
2058#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos)
2060#define ADC_OFR2_OFFSET2_CH_Pos (26U)
2061#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
2062#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
2063#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
2064#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
2065#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
2066#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
2067#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
2069#define ADC_OFR2_OFFSET2_EN_Pos (31U)
2070#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)
2071#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk
2073/******************** Bit definition for ADC_OFR3 register ******************/
2074#define ADC_OFR3_OFFSET3_Pos (0U)
2075#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)
2076#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
2077#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos)
2078#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos)
2079#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos)
2080#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos)
2081#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos)
2082#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos)
2083#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos)
2084#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos)
2085#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos)
2086#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos)
2087#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos)
2088#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos)
2090#define ADC_OFR3_OFFSET3_CH_Pos (26U)
2091#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
2092#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
2093#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
2094#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
2095#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
2096#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
2097#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
2099#define ADC_OFR3_OFFSET3_EN_Pos (31U)
2100#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)
2101#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk
2103/******************** Bit definition for ADC_OFR4 register ******************/
2104#define ADC_OFR4_OFFSET4_Pos (0U)
2105#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)
2106#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
2107#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos)
2108#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos)
2109#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos)
2110#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos)
2111#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos)
2112#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos)
2113#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos)
2114#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos)
2115#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos)
2116#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos)
2117#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos)
2118#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos)
2120#define ADC_OFR4_OFFSET4_CH_Pos (26U)
2121#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
2122#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
2123#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
2124#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
2125#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
2126#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
2127#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
2129#define ADC_OFR4_OFFSET4_EN_Pos (31U)
2130#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)
2131#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk
2133/******************** Bit definition for ADC_JDR1 register ******************/
2134#define ADC_JDR1_JDATA_Pos (0U)
2135#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
2136#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
2137#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos)
2138#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos)
2139#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos)
2140#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos)
2141#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos)
2142#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos)
2143#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos)
2144#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos)
2145#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos)
2146#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos)
2147#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos)
2148#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos)
2149#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos)
2150#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos)
2151#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos)
2152#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos)
2154/******************** Bit definition for ADC_JDR2 register ******************/
2155#define ADC_JDR2_JDATA_Pos (0U)
2156#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
2157#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
2158#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos)
2159#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos)
2160#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos)
2161#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos)
2162#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos)
2163#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos)
2164#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos)
2165#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos)
2166#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos)
2167#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos)
2168#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos)
2169#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos)
2170#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos)
2171#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos)
2172#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos)
2173#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos)
2175/******************** Bit definition for ADC_JDR3 register ******************/
2176#define ADC_JDR3_JDATA_Pos (0U)
2177#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
2178#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
2179#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos)
2180#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos)
2181#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos)
2182#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos)
2183#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos)
2184#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos)
2185#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos)
2186#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos)
2187#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos)
2188#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos)
2189#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos)
2190#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos)
2191#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos)
2192#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos)
2193#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos)
2194#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos)
2196/******************** Bit definition for ADC_JDR4 register ******************/
2197#define ADC_JDR4_JDATA_Pos (0U)
2198#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
2199#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
2200#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos)
2201#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos)
2202#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos)
2203#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos)
2204#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos)
2205#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos)
2206#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos)
2207#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos)
2208#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos)
2209#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos)
2210#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos)
2211#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos)
2212#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos)
2213#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos)
2214#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos)
2215#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos)
2217/******************** Bit definition for ADC_AWD2CR register ****************/
2218#define ADC_AWD2CR_AWD2CH_Pos (0U)
2219#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)
2220#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
2221#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
2222#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
2223#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
2224#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
2225#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
2226#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
2227#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
2228#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
2229#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
2230#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
2231#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
2232#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
2233#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
2234#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
2235#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
2236#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
2237#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
2238#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
2239#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
2241/******************** Bit definition for ADC_AWD3CR register ****************/
2242#define ADC_AWD3CR_AWD3CH_Pos (0U)
2243#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)
2244#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
2245#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
2246#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
2247#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
2248#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
2249#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
2250#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
2251#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
2252#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
2253#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
2254#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
2255#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
2256#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
2257#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
2258#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
2259#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
2260#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
2261#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
2262#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
2263#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
2265/******************** Bit definition for ADC_DIFSEL register ****************/
2266#define ADC_DIFSEL_DIFSEL_Pos (0U)
2267#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)
2268#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
2269#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
2270#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
2271#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
2272#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
2273#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
2274#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
2275#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
2276#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
2277#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
2278#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
2279#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
2280#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
2281#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
2282#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
2283#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
2284#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
2285#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
2286#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
2287#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
2289/******************** Bit definition for ADC_CALFACT register ***************/
2290#define ADC_CALFACT_CALFACT_S_Pos (0U)
2291#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)
2292#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
2293#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)
2294#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)
2295#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)
2296#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)
2297#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)
2298#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)
2299#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)
2301#define ADC_CALFACT_CALFACT_D_Pos (16U)
2302#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)
2303#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
2304#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)
2305#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)
2306#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)
2307#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)
2308#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)
2309#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)
2310#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)
2312/************************* ADC Common registers *****************************/
2313/******************** Bit definition for ADC_CSR register *******************/
2314#define ADC_CSR_ADRDY_MST_Pos (0U)
2315#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
2316#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
2317#define ADC_CSR_EOSMP_MST_Pos (1U)
2318#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
2319#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
2320#define ADC_CSR_EOC_MST_Pos (2U)
2321#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
2322#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
2323#define ADC_CSR_EOS_MST_Pos (3U)
2324#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
2325#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
2326#define ADC_CSR_OVR_MST_Pos (4U)
2327#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
2328#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
2329#define ADC_CSR_JEOC_MST_Pos (5U)
2330#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
2331#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
2332#define ADC_CSR_JEOS_MST_Pos (6U)
2333#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
2334#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
2335#define ADC_CSR_AWD1_MST_Pos (7U)
2336#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
2337#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
2338#define ADC_CSR_AWD2_MST_Pos (8U)
2339#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
2340#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
2341#define ADC_CSR_AWD3_MST_Pos (9U)
2342#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
2343#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
2344#define ADC_CSR_JQOVF_MST_Pos (10U)
2345#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
2346#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
2348#define ADC_CSR_ADRDY_SLV_Pos (16U)
2349#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
2350#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
2351#define ADC_CSR_EOSMP_SLV_Pos (17U)
2352#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
2353#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
2354#define ADC_CSR_EOC_SLV_Pos (18U)
2355#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
2356#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
2357#define ADC_CSR_EOS_SLV_Pos (19U)
2358#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
2359#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
2360#define ADC_CSR_OVR_SLV_Pos (20U)
2361#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
2362#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
2363#define ADC_CSR_JEOC_SLV_Pos (21U)
2364#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
2365#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
2366#define ADC_CSR_JEOS_SLV_Pos (22U)
2367#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
2368#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
2369#define ADC_CSR_AWD1_SLV_Pos (23U)
2370#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
2371#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
2372#define ADC_CSR_AWD2_SLV_Pos (24U)
2373#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
2374#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
2375#define ADC_CSR_AWD3_SLV_Pos (25U)
2376#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
2377#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
2378#define ADC_CSR_JQOVF_SLV_Pos (26U)
2379#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
2380#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
2382/******************** Bit definition for ADC_CCR register *******************/
2383#define ADC_CCR_DUAL_Pos (0U)
2384#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
2385#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
2386#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
2387#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
2388#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
2389#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
2390#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
2392#define ADC_CCR_DELAY_Pos (8U)
2393#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
2394#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
2395#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
2396#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
2397#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
2398#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
2400#define ADC_CCR_DMACFG_Pos (13U)
2401#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)
2402#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk
2404#define ADC_CCR_MDMA_Pos (14U)
2405#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)
2406#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk
2407#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)
2408#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)
2410#define ADC_CCR_CKMODE_Pos (16U)
2411#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
2412#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
2413#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
2414#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
2416#define ADC_CCR_PRESC_Pos (18U)
2417#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
2418#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
2419#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
2420#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
2421#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
2422#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
2424#define ADC_CCR_VREFEN_Pos (22U)
2425#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
2426#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
2427#define ADC_CCR_TSEN_Pos (23U)
2428#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
2429#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
2430#define ADC_CCR_VBATEN_Pos (24U)
2431#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
2432#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
2434/******************** Bit definition for ADC_CDR register *******************/
2435#define ADC_CDR_RDATA_MST_Pos (0U)
2436#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
2437#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
2438#define ADC_CDR_RDATA_MST_0 (0x0001UL << ADC_CDR_RDATA_MST_Pos)
2439#define ADC_CDR_RDATA_MST_1 (0x0002UL << ADC_CDR_RDATA_MST_Pos)
2440#define ADC_CDR_RDATA_MST_2 (0x0004UL << ADC_CDR_RDATA_MST_Pos)
2441#define ADC_CDR_RDATA_MST_3 (0x0008UL << ADC_CDR_RDATA_MST_Pos)
2442#define ADC_CDR_RDATA_MST_4 (0x0010UL << ADC_CDR_RDATA_MST_Pos)
2443#define ADC_CDR_RDATA_MST_5 (0x0020UL << ADC_CDR_RDATA_MST_Pos)
2444#define ADC_CDR_RDATA_MST_6 (0x0040UL << ADC_CDR_RDATA_MST_Pos)
2445#define ADC_CDR_RDATA_MST_7 (0x0080UL << ADC_CDR_RDATA_MST_Pos)
2446#define ADC_CDR_RDATA_MST_8 (0x0100UL << ADC_CDR_RDATA_MST_Pos)
2447#define ADC_CDR_RDATA_MST_9 (0x0200UL << ADC_CDR_RDATA_MST_Pos)
2448#define ADC_CDR_RDATA_MST_10 (0x0400UL << ADC_CDR_RDATA_MST_Pos)
2449#define ADC_CDR_RDATA_MST_11 (0x0800UL << ADC_CDR_RDATA_MST_Pos)
2450#define ADC_CDR_RDATA_MST_12 (0x1000UL << ADC_CDR_RDATA_MST_Pos)
2451#define ADC_CDR_RDATA_MST_13 (0x2000UL << ADC_CDR_RDATA_MST_Pos)
2452#define ADC_CDR_RDATA_MST_14 (0x4000UL << ADC_CDR_RDATA_MST_Pos)
2453#define ADC_CDR_RDATA_MST_15 (0x8000UL << ADC_CDR_RDATA_MST_Pos)
2455#define ADC_CDR_RDATA_SLV_Pos (16U)
2456#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
2457#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
2458#define ADC_CDR_RDATA_SLV_0 (0x0001UL << ADC_CDR_RDATA_SLV_Pos)
2459#define ADC_CDR_RDATA_SLV_1 (0x0002UL << ADC_CDR_RDATA_SLV_Pos)
2460#define ADC_CDR_RDATA_SLV_2 (0x0004UL << ADC_CDR_RDATA_SLV_Pos)
2461#define ADC_CDR_RDATA_SLV_3 (0x0008UL << ADC_CDR_RDATA_SLV_Pos)
2462#define ADC_CDR_RDATA_SLV_4 (0x0010UL << ADC_CDR_RDATA_SLV_Pos)
2463#define ADC_CDR_RDATA_SLV_5 (0x0020UL << ADC_CDR_RDATA_SLV_Pos)
2464#define ADC_CDR_RDATA_SLV_6 (0x0040UL << ADC_CDR_RDATA_SLV_Pos)
2465#define ADC_CDR_RDATA_SLV_7 (0x0080UL << ADC_CDR_RDATA_SLV_Pos)
2466#define ADC_CDR_RDATA_SLV_8 (0x0100UL << ADC_CDR_RDATA_SLV_Pos)
2467#define ADC_CDR_RDATA_SLV_9 (0x0200UL << ADC_CDR_RDATA_SLV_Pos)
2468#define ADC_CDR_RDATA_SLV_10 (0x0400UL << ADC_CDR_RDATA_SLV_Pos)
2469#define ADC_CDR_RDATA_SLV_11 (0x0800UL << ADC_CDR_RDATA_SLV_Pos)
2470#define ADC_CDR_RDATA_SLV_12 (0x1000UL << ADC_CDR_RDATA_SLV_Pos)
2471#define ADC_CDR_RDATA_SLV_13 (0x2000UL << ADC_CDR_RDATA_SLV_Pos)
2472#define ADC_CDR_RDATA_SLV_14 (0x4000UL << ADC_CDR_RDATA_SLV_Pos)
2473#define ADC_CDR_RDATA_SLV_15 (0x8000UL << ADC_CDR_RDATA_SLV_Pos)
2475/******************************************************************************/
2476/* */
2477/* Controller Area Network */
2478/* */
2479/******************************************************************************/
2481/******************* Bit definition for CAN_MCR register ********************/
2482#define CAN_MCR_INRQ_Pos (0U)
2483#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2484#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2485#define CAN_MCR_SLEEP_Pos (1U)
2486#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2487#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2488#define CAN_MCR_TXFP_Pos (2U)
2489#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2490#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2491#define CAN_MCR_RFLM_Pos (3U)
2492#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2493#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2494#define CAN_MCR_NART_Pos (4U)
2495#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2496#define CAN_MCR_NART CAN_MCR_NART_Msk
2497#define CAN_MCR_AWUM_Pos (5U)
2498#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2499#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2500#define CAN_MCR_ABOM_Pos (6U)
2501#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2502#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2503#define CAN_MCR_TTCM_Pos (7U)
2504#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2505#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2506#define CAN_MCR_RESET_Pos (15U)
2507#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2508#define CAN_MCR_RESET CAN_MCR_RESET_Msk
2510/******************* Bit definition for CAN_MSR register ********************/
2511#define CAN_MSR_INAK_Pos (0U)
2512#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2513#define CAN_MSR_INAK CAN_MSR_INAK_Msk
2514#define CAN_MSR_SLAK_Pos (1U)
2515#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2516#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2517#define CAN_MSR_ERRI_Pos (2U)
2518#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2519#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2520#define CAN_MSR_WKUI_Pos (3U)
2521#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2522#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2523#define CAN_MSR_SLAKI_Pos (4U)
2524#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2525#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2526#define CAN_MSR_TXM_Pos (8U)
2527#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2528#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2529#define CAN_MSR_RXM_Pos (9U)
2530#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2531#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2532#define CAN_MSR_SAMP_Pos (10U)
2533#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2534#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2535#define CAN_MSR_RX_Pos (11U)
2536#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2537#define CAN_MSR_RX CAN_MSR_RX_Msk
2539/******************* Bit definition for CAN_TSR register ********************/
2540#define CAN_TSR_RQCP0_Pos (0U)
2541#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2542#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2543#define CAN_TSR_TXOK0_Pos (1U)
2544#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2545#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2546#define CAN_TSR_ALST0_Pos (2U)
2547#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2548#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2549#define CAN_TSR_TERR0_Pos (3U)
2550#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2551#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2552#define CAN_TSR_ABRQ0_Pos (7U)
2553#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2554#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2555#define CAN_TSR_RQCP1_Pos (8U)
2556#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2557#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2558#define CAN_TSR_TXOK1_Pos (9U)
2559#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2560#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2561#define CAN_TSR_ALST1_Pos (10U)
2562#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2563#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2564#define CAN_TSR_TERR1_Pos (11U)
2565#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2566#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2567#define CAN_TSR_ABRQ1_Pos (15U)
2568#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2569#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2570#define CAN_TSR_RQCP2_Pos (16U)
2571#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2572#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2573#define CAN_TSR_TXOK2_Pos (17U)
2574#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2575#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2576#define CAN_TSR_ALST2_Pos (18U)
2577#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2578#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2579#define CAN_TSR_TERR2_Pos (19U)
2580#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2581#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2582#define CAN_TSR_ABRQ2_Pos (23U)
2583#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2584#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2585#define CAN_TSR_CODE_Pos (24U)
2586#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2587#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2589#define CAN_TSR_TME_Pos (26U)
2590#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2591#define CAN_TSR_TME CAN_TSR_TME_Msk
2592#define CAN_TSR_TME0_Pos (26U)
2593#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2594#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2595#define CAN_TSR_TME1_Pos (27U)
2596#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2597#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2598#define CAN_TSR_TME2_Pos (28U)
2599#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2600#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2602#define CAN_TSR_LOW_Pos (29U)
2603#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2604#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2605#define CAN_TSR_LOW0_Pos (29U)
2606#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2607#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2608#define CAN_TSR_LOW1_Pos (30U)
2609#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2610#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2611#define CAN_TSR_LOW2_Pos (31U)
2612#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2613#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2615/******************* Bit definition for CAN_RF0R register *******************/
2616#define CAN_RF0R_FMP0_Pos (0U)
2617#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2618#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2619#define CAN_RF0R_FULL0_Pos (3U)
2620#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2621#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2622#define CAN_RF0R_FOVR0_Pos (4U)
2623#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2624#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2625#define CAN_RF0R_RFOM0_Pos (5U)
2626#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2627#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2629/******************* Bit definition for CAN_RF1R register *******************/
2630#define CAN_RF1R_FMP1_Pos (0U)
2631#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2632#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2633#define CAN_RF1R_FULL1_Pos (3U)
2634#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2635#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2636#define CAN_RF1R_FOVR1_Pos (4U)
2637#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2638#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2639#define CAN_RF1R_RFOM1_Pos (5U)
2640#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2641#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2643/******************** Bit definition for CAN_IER register *******************/
2644#define CAN_IER_TMEIE_Pos (0U)
2645#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2646#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2647#define CAN_IER_FMPIE0_Pos (1U)
2648#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2649#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2650#define CAN_IER_FFIE0_Pos (2U)
2651#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2652#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2653#define CAN_IER_FOVIE0_Pos (3U)
2654#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2655#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2656#define CAN_IER_FMPIE1_Pos (4U)
2657#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2658#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2659#define CAN_IER_FFIE1_Pos (5U)
2660#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2661#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2662#define CAN_IER_FOVIE1_Pos (6U)
2663#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2664#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2665#define CAN_IER_EWGIE_Pos (8U)
2666#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2667#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2668#define CAN_IER_EPVIE_Pos (9U)
2669#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2670#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2671#define CAN_IER_BOFIE_Pos (10U)
2672#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2673#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2674#define CAN_IER_LECIE_Pos (11U)
2675#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2676#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2677#define CAN_IER_ERRIE_Pos (15U)
2678#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2679#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2680#define CAN_IER_WKUIE_Pos (16U)
2681#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2682#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2683#define CAN_IER_SLKIE_Pos (17U)
2684#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2685#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2687/******************** Bit definition for CAN_ESR register *******************/
2688#define CAN_ESR_EWGF_Pos (0U)
2689#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2690#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2691#define CAN_ESR_EPVF_Pos (1U)
2692#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2693#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2694#define CAN_ESR_BOFF_Pos (2U)
2695#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2696#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2698#define CAN_ESR_LEC_Pos (4U)
2699#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2700#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2701#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2702#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2703#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2705#define CAN_ESR_TEC_Pos (16U)
2706#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2707#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2708#define CAN_ESR_REC_Pos (24U)
2709#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2710#define CAN_ESR_REC CAN_ESR_REC_Msk
2712/******************* Bit definition for CAN_BTR register ********************/
2713#define CAN_BTR_BRP_Pos (0U)
2714#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2715#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2716#define CAN_BTR_TS1_Pos (16U)
2717#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2718#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2719#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2720#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2721#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2722#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2723#define CAN_BTR_TS2_Pos (20U)
2724#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2725#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2726#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2727#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2728#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2729#define CAN_BTR_SJW_Pos (24U)
2730#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2731#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2732#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2733#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2734#define CAN_BTR_LBKM_Pos (30U)
2735#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2736#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2737#define CAN_BTR_SILM_Pos (31U)
2738#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2739#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2742/****************** Bit definition for CAN_TI0R register ********************/
2743#define CAN_TI0R_TXRQ_Pos (0U)
2744#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2745#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2746#define CAN_TI0R_RTR_Pos (1U)
2747#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2748#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2749#define CAN_TI0R_IDE_Pos (2U)
2750#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2751#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2752#define CAN_TI0R_EXID_Pos (3U)
2753#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2754#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2755#define CAN_TI0R_STID_Pos (21U)
2756#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2757#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2759/****************** Bit definition for CAN_TDT0R register *******************/
2760#define CAN_TDT0R_DLC_Pos (0U)
2761#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2762#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2763#define CAN_TDT0R_TGT_Pos (8U)
2764#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2765#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2766#define CAN_TDT0R_TIME_Pos (16U)
2767#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2768#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2770/****************** Bit definition for CAN_TDL0R register *******************/
2771#define CAN_TDL0R_DATA0_Pos (0U)
2772#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2773#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2774#define CAN_TDL0R_DATA1_Pos (8U)
2775#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2776#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2777#define CAN_TDL0R_DATA2_Pos (16U)
2778#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2779#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2780#define CAN_TDL0R_DATA3_Pos (24U)
2781#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2782#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2784/****************** Bit definition for CAN_TDH0R register *******************/
2785#define CAN_TDH0R_DATA4_Pos (0U)
2786#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2787#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2788#define CAN_TDH0R_DATA5_Pos (8U)
2789#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2790#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2791#define CAN_TDH0R_DATA6_Pos (16U)
2792#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2793#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2794#define CAN_TDH0R_DATA7_Pos (24U)
2795#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2796#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2798/******************* Bit definition for CAN_TI1R register *******************/
2799#define CAN_TI1R_TXRQ_Pos (0U)
2800#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2801#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2802#define CAN_TI1R_RTR_Pos (1U)
2803#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2804#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2805#define CAN_TI1R_IDE_Pos (2U)
2806#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2807#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2808#define CAN_TI1R_EXID_Pos (3U)
2809#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2810#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2811#define CAN_TI1R_STID_Pos (21U)
2812#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2813#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2815/******************* Bit definition for CAN_TDT1R register ******************/
2816#define CAN_TDT1R_DLC_Pos (0U)
2817#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2818#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2819#define CAN_TDT1R_TGT_Pos (8U)
2820#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2821#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2822#define CAN_TDT1R_TIME_Pos (16U)
2823#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2824#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2826/******************* Bit definition for CAN_TDL1R register ******************/
2827#define CAN_TDL1R_DATA0_Pos (0U)
2828#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2829#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2830#define CAN_TDL1R_DATA1_Pos (8U)
2831#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2832#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2833#define CAN_TDL1R_DATA2_Pos (16U)
2834#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2835#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2836#define CAN_TDL1R_DATA3_Pos (24U)
2837#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2838#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2840/******************* Bit definition for CAN_TDH1R register ******************/
2841#define CAN_TDH1R_DATA4_Pos (0U)
2842#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2843#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2844#define CAN_TDH1R_DATA5_Pos (8U)
2845#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2846#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2847#define CAN_TDH1R_DATA6_Pos (16U)
2848#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2849#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2850#define CAN_TDH1R_DATA7_Pos (24U)
2851#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2852#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2854/******************* Bit definition for CAN_TI2R register *******************/
2855#define CAN_TI2R_TXRQ_Pos (0U)
2856#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2857#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2858#define CAN_TI2R_RTR_Pos (1U)
2859#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2860#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2861#define CAN_TI2R_IDE_Pos (2U)
2862#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2863#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2864#define CAN_TI2R_EXID_Pos (3U)
2865#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2866#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2867#define CAN_TI2R_STID_Pos (21U)
2868#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2869#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2871/******************* Bit definition for CAN_TDT2R register ******************/
2872#define CAN_TDT2R_DLC_Pos (0U)
2873#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2874#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2875#define CAN_TDT2R_TGT_Pos (8U)
2876#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2877#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2878#define CAN_TDT2R_TIME_Pos (16U)
2879#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2880#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2882/******************* Bit definition for CAN_TDL2R register ******************/
2883#define CAN_TDL2R_DATA0_Pos (0U)
2884#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2885#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2886#define CAN_TDL2R_DATA1_Pos (8U)
2887#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2888#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2889#define CAN_TDL2R_DATA2_Pos (16U)
2890#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2891#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2892#define CAN_TDL2R_DATA3_Pos (24U)
2893#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2894#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2896/******************* Bit definition for CAN_TDH2R register ******************/
2897#define CAN_TDH2R_DATA4_Pos (0U)
2898#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2899#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2900#define CAN_TDH2R_DATA5_Pos (8U)
2901#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2902#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2903#define CAN_TDH2R_DATA6_Pos (16U)
2904#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2905#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2906#define CAN_TDH2R_DATA7_Pos (24U)
2907#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2908#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2910/******************* Bit definition for CAN_RI0R register *******************/
2911#define CAN_RI0R_RTR_Pos (1U)
2912#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2913#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2914#define CAN_RI0R_IDE_Pos (2U)
2915#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2916#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2917#define CAN_RI0R_EXID_Pos (3U)
2918#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2919#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2920#define CAN_RI0R_STID_Pos (21U)
2921#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2922#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2924/******************* Bit definition for CAN_RDT0R register ******************/
2925#define CAN_RDT0R_DLC_Pos (0U)
2926#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2927#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2928#define CAN_RDT0R_FMI_Pos (8U)
2929#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2930#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2931#define CAN_RDT0R_TIME_Pos (16U)
2932#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2933#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2935/******************* Bit definition for CAN_RDL0R register ******************/
2936#define CAN_RDL0R_DATA0_Pos (0U)
2937#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2938#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2939#define CAN_RDL0R_DATA1_Pos (8U)
2940#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2941#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2942#define CAN_RDL0R_DATA2_Pos (16U)
2943#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2944#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2945#define CAN_RDL0R_DATA3_Pos (24U)
2946#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2947#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2949/******************* Bit definition for CAN_RDH0R register ******************/
2950#define CAN_RDH0R_DATA4_Pos (0U)
2951#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2952#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2953#define CAN_RDH0R_DATA5_Pos (8U)
2954#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2955#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2956#define CAN_RDH0R_DATA6_Pos (16U)
2957#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2958#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2959#define CAN_RDH0R_DATA7_Pos (24U)
2960#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2961#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2963/******************* Bit definition for CAN_RI1R register *******************/
2964#define CAN_RI1R_RTR_Pos (1U)
2965#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2966#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2967#define CAN_RI1R_IDE_Pos (2U)
2968#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2969#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2970#define CAN_RI1R_EXID_Pos (3U)
2971#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2972#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2973#define CAN_RI1R_STID_Pos (21U)
2974#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2975#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2977/******************* Bit definition for CAN_RDT1R register ******************/
2978#define CAN_RDT1R_DLC_Pos (0U)
2979#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2980#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2981#define CAN_RDT1R_FMI_Pos (8U)
2982#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2983#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2984#define CAN_RDT1R_TIME_Pos (16U)
2985#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2986#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2988/******************* Bit definition for CAN_RDL1R register ******************/
2989#define CAN_RDL1R_DATA0_Pos (0U)
2990#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2991#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2992#define CAN_RDL1R_DATA1_Pos (8U)
2993#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2994#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2995#define CAN_RDL1R_DATA2_Pos (16U)
2996#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2997#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2998#define CAN_RDL1R_DATA3_Pos (24U)
2999#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
3000#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
3002/******************* Bit definition for CAN_RDH1R register ******************/
3003#define CAN_RDH1R_DATA4_Pos (0U)
3004#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
3005#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
3006#define CAN_RDH1R_DATA5_Pos (8U)
3007#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
3008#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
3009#define CAN_RDH1R_DATA6_Pos (16U)
3010#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
3011#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
3012#define CAN_RDH1R_DATA7_Pos (24U)
3013#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
3014#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
3017/******************* Bit definition for CAN_FMR register ********************/
3018#define CAN_FMR_FINIT_Pos (0U)
3019#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
3020#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
3022/******************* Bit definition for CAN_FM1R register *******************/
3023#define CAN_FM1R_FBM_Pos (0U)
3024#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
3025#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
3026#define CAN_FM1R_FBM0_Pos (0U)
3027#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
3028#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
3029#define CAN_FM1R_FBM1_Pos (1U)
3030#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
3031#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
3032#define CAN_FM1R_FBM2_Pos (2U)
3033#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
3034#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
3035#define CAN_FM1R_FBM3_Pos (3U)
3036#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
3037#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
3038#define CAN_FM1R_FBM4_Pos (4U)
3039#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
3040#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
3041#define CAN_FM1R_FBM5_Pos (5U)
3042#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
3043#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
3044#define CAN_FM1R_FBM6_Pos (6U)
3045#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
3046#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
3047#define CAN_FM1R_FBM7_Pos (7U)
3048#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
3049#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
3050#define CAN_FM1R_FBM8_Pos (8U)
3051#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
3052#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
3053#define CAN_FM1R_FBM9_Pos (9U)
3054#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
3055#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
3056#define CAN_FM1R_FBM10_Pos (10U)
3057#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
3058#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
3059#define CAN_FM1R_FBM11_Pos (11U)
3060#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
3061#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
3062#define CAN_FM1R_FBM12_Pos (12U)
3063#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
3064#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
3065#define CAN_FM1R_FBM13_Pos (13U)
3066#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
3067#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
3069/******************* Bit definition for CAN_FS1R register *******************/
3070#define CAN_FS1R_FSC_Pos (0U)
3071#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
3072#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
3073#define CAN_FS1R_FSC0_Pos (0U)
3074#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
3075#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
3076#define CAN_FS1R_FSC1_Pos (1U)
3077#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
3078#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
3079#define CAN_FS1R_FSC2_Pos (2U)
3080#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
3081#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
3082#define CAN_FS1R_FSC3_Pos (3U)
3083#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
3084#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
3085#define CAN_FS1R_FSC4_Pos (4U)
3086#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
3087#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
3088#define CAN_FS1R_FSC5_Pos (5U)
3089#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
3090#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
3091#define CAN_FS1R_FSC6_Pos (6U)
3092#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
3093#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
3094#define CAN_FS1R_FSC7_Pos (7U)
3095#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
3096#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
3097#define CAN_FS1R_FSC8_Pos (8U)
3098#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
3099#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
3100#define CAN_FS1R_FSC9_Pos (9U)
3101#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
3102#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
3103#define CAN_FS1R_FSC10_Pos (10U)
3104#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
3105#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
3106#define CAN_FS1R_FSC11_Pos (11U)
3107#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
3108#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
3109#define CAN_FS1R_FSC12_Pos (12U)
3110#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
3111#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
3112#define CAN_FS1R_FSC13_Pos (13U)
3113#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
3114#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
3116/****************** Bit definition for CAN_FFA1R register *******************/
3117#define CAN_FFA1R_FFA_Pos (0U)
3118#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
3119#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
3120#define CAN_FFA1R_FFA0_Pos (0U)
3121#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
3122#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
3123#define CAN_FFA1R_FFA1_Pos (1U)
3124#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
3125#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
3126#define CAN_FFA1R_FFA2_Pos (2U)
3127#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
3128#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
3129#define CAN_FFA1R_FFA3_Pos (3U)
3130#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
3131#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
3132#define CAN_FFA1R_FFA4_Pos (4U)
3133#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
3134#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
3135#define CAN_FFA1R_FFA5_Pos (5U)
3136#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
3137#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
3138#define CAN_FFA1R_FFA6_Pos (6U)
3139#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
3140#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
3141#define CAN_FFA1R_FFA7_Pos (7U)
3142#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
3143#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
3144#define CAN_FFA1R_FFA8_Pos (8U)
3145#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
3146#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
3147#define CAN_FFA1R_FFA9_Pos (9U)
3148#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
3149#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
3150#define CAN_FFA1R_FFA10_Pos (10U)
3151#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
3152#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
3153#define CAN_FFA1R_FFA11_Pos (11U)
3154#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
3155#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
3156#define CAN_FFA1R_FFA12_Pos (12U)
3157#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
3158#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
3159#define CAN_FFA1R_FFA13_Pos (13U)
3160#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
3161#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
3163/******************* Bit definition for CAN_FA1R register *******************/
3164#define CAN_FA1R_FACT_Pos (0U)
3165#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
3166#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
3167#define CAN_FA1R_FACT0_Pos (0U)
3168#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
3169#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
3170#define CAN_FA1R_FACT1_Pos (1U)
3171#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
3172#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
3173#define CAN_FA1R_FACT2_Pos (2U)
3174#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
3175#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
3176#define CAN_FA1R_FACT3_Pos (3U)
3177#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
3178#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
3179#define CAN_FA1R_FACT4_Pos (4U)
3180#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
3181#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
3182#define CAN_FA1R_FACT5_Pos (5U)
3183#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
3184#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
3185#define CAN_FA1R_FACT6_Pos (6U)
3186#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
3187#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
3188#define CAN_FA1R_FACT7_Pos (7U)
3189#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
3190#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
3191#define CAN_FA1R_FACT8_Pos (8U)
3192#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
3193#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
3194#define CAN_FA1R_FACT9_Pos (9U)
3195#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
3196#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
3197#define CAN_FA1R_FACT10_Pos (10U)
3198#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
3199#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
3200#define CAN_FA1R_FACT11_Pos (11U)
3201#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
3202#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
3203#define CAN_FA1R_FACT12_Pos (12U)
3204#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
3205#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
3206#define CAN_FA1R_FACT13_Pos (13U)
3207#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
3208#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
3210/******************* Bit definition for CAN_F0R1 register *******************/
3211#define CAN_F0R1_FB0_Pos (0U)
3212#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
3213#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
3214#define CAN_F0R1_FB1_Pos (1U)
3215#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
3216#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
3217#define CAN_F0R1_FB2_Pos (2U)
3218#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
3219#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
3220#define CAN_F0R1_FB3_Pos (3U)
3221#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
3222#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
3223#define CAN_F0R1_FB4_Pos (4U)
3224#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
3225#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
3226#define CAN_F0R1_FB5_Pos (5U)
3227#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
3228#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
3229#define CAN_F0R1_FB6_Pos (6U)
3230#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
3231#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
3232#define CAN_F0R1_FB7_Pos (7U)
3233#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
3234#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
3235#define CAN_F0R1_FB8_Pos (8U)
3236#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
3237#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
3238#define CAN_F0R1_FB9_Pos (9U)
3239#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
3240#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
3241#define CAN_F0R1_FB10_Pos (10U)
3242#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
3243#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
3244#define CAN_F0R1_FB11_Pos (11U)
3245#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
3246#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
3247#define CAN_F0R1_FB12_Pos (12U)
3248#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
3249#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
3250#define CAN_F0R1_FB13_Pos (13U)
3251#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
3252#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
3253#define CAN_F0R1_FB14_Pos (14U)
3254#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
3255#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
3256#define CAN_F0R1_FB15_Pos (15U)
3257#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
3258#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
3259#define CAN_F0R1_FB16_Pos (16U)
3260#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
3261#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
3262#define CAN_F0R1_FB17_Pos (17U)
3263#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
3264#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
3265#define CAN_F0R1_FB18_Pos (18U)
3266#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
3267#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
3268#define CAN_F0R1_FB19_Pos (19U)
3269#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
3270#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
3271#define CAN_F0R1_FB20_Pos (20U)
3272#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
3273#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
3274#define CAN_F0R1_FB21_Pos (21U)
3275#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
3276#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
3277#define CAN_F0R1_FB22_Pos (22U)
3278#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
3279#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
3280#define CAN_F0R1_FB23_Pos (23U)
3281#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
3282#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
3283#define CAN_F0R1_FB24_Pos (24U)
3284#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
3285#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
3286#define CAN_F0R1_FB25_Pos (25U)
3287#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
3288#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
3289#define CAN_F0R1_FB26_Pos (26U)
3290#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
3291#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
3292#define CAN_F0R1_FB27_Pos (27U)
3293#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
3294#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
3295#define CAN_F0R1_FB28_Pos (28U)
3296#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
3297#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
3298#define CAN_F0R1_FB29_Pos (29U)
3299#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
3300#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
3301#define CAN_F0R1_FB30_Pos (30U)
3302#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
3303#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
3304#define CAN_F0R1_FB31_Pos (31U)
3305#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
3306#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3308/******************* Bit definition for CAN_F1R1 register *******************/
3309#define CAN_F1R1_FB0_Pos (0U)
3310#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3311#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3312#define CAN_F1R1_FB1_Pos (1U)
3313#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3314#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3315#define CAN_F1R1_FB2_Pos (2U)
3316#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3317#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3318#define CAN_F1R1_FB3_Pos (3U)
3319#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3320#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3321#define CAN_F1R1_FB4_Pos (4U)
3322#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3323#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3324#define CAN_F1R1_FB5_Pos (5U)
3325#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3326#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3327#define CAN_F1R1_FB6_Pos (6U)
3328#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3329#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3330#define CAN_F1R1_FB7_Pos (7U)
3331#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3332#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3333#define CAN_F1R1_FB8_Pos (8U)
3334#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3335#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3336#define CAN_F1R1_FB9_Pos (9U)
3337#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3338#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3339#define CAN_F1R1_FB10_Pos (10U)
3340#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3341#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3342#define CAN_F1R1_FB11_Pos (11U)
3343#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3344#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3345#define CAN_F1R1_FB12_Pos (12U)
3346#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3347#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3348#define CAN_F1R1_FB13_Pos (13U)
3349#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3350#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3351#define CAN_F1R1_FB14_Pos (14U)
3352#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3353#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3354#define CAN_F1R1_FB15_Pos (15U)
3355#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3356#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3357#define CAN_F1R1_FB16_Pos (16U)
3358#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3359#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3360#define CAN_F1R1_FB17_Pos (17U)
3361#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3362#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3363#define CAN_F1R1_FB18_Pos (18U)
3364#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3365#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3366#define CAN_F1R1_FB19_Pos (19U)
3367#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3368#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3369#define CAN_F1R1_FB20_Pos (20U)
3370#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3371#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3372#define CAN_F1R1_FB21_Pos (21U)
3373#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3374#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3375#define CAN_F1R1_FB22_Pos (22U)
3376#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3377#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3378#define CAN_F1R1_FB23_Pos (23U)
3379#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3380#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3381#define CAN_F1R1_FB24_Pos (24U)
3382#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3383#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3384#define CAN_F1R1_FB25_Pos (25U)
3385#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3386#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3387#define CAN_F1R1_FB26_Pos (26U)
3388#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3389#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3390#define CAN_F1R1_FB27_Pos (27U)
3391#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3392#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3393#define CAN_F1R1_FB28_Pos (28U)
3394#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3395#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3396#define CAN_F1R1_FB29_Pos (29U)
3397#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3398#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3399#define CAN_F1R1_FB30_Pos (30U)
3400#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3401#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3402#define CAN_F1R1_FB31_Pos (31U)
3403#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3404#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3406/******************* Bit definition for CAN_F2R1 register *******************/
3407#define CAN_F2R1_FB0_Pos (0U)
3408#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3409#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3410#define CAN_F2R1_FB1_Pos (1U)
3411#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3412#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3413#define CAN_F2R1_FB2_Pos (2U)
3414#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3415#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3416#define CAN_F2R1_FB3_Pos (3U)
3417#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3418#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3419#define CAN_F2R1_FB4_Pos (4U)
3420#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3421#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3422#define CAN_F2R1_FB5_Pos (5U)
3423#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3424#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3425#define CAN_F2R1_FB6_Pos (6U)
3426#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3427#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3428#define CAN_F2R1_FB7_Pos (7U)
3429#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3430#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3431#define CAN_F2R1_FB8_Pos (8U)
3432#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3433#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3434#define CAN_F2R1_FB9_Pos (9U)
3435#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3436#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3437#define CAN_F2R1_FB10_Pos (10U)
3438#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3439#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3440#define CAN_F2R1_FB11_Pos (11U)
3441#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3442#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3443#define CAN_F2R1_FB12_Pos (12U)
3444#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3445#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3446#define CAN_F2R1_FB13_Pos (13U)
3447#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3448#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3449#define CAN_F2R1_FB14_Pos (14U)
3450#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3451#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3452#define CAN_F2R1_FB15_Pos (15U)
3453#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3454#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3455#define CAN_F2R1_FB16_Pos (16U)
3456#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3457#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3458#define CAN_F2R1_FB17_Pos (17U)
3459#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3460#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3461#define CAN_F2R1_FB18_Pos (18U)
3462#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3463#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3464#define CAN_F2R1_FB19_Pos (19U)
3465#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3466#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3467#define CAN_F2R1_FB20_Pos (20U)
3468#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3469#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3470#define CAN_F2R1_FB21_Pos (21U)
3471#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3472#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3473#define CAN_F2R1_FB22_Pos (22U)
3474#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3475#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3476#define CAN_F2R1_FB23_Pos (23U)
3477#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3478#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3479#define CAN_F2R1_FB24_Pos (24U)
3480#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3481#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3482#define CAN_F2R1_FB25_Pos (25U)
3483#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3484#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3485#define CAN_F2R1_FB26_Pos (26U)
3486#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3487#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3488#define CAN_F2R1_FB27_Pos (27U)
3489#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3490#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3491#define CAN_F2R1_FB28_Pos (28U)
3492#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3493#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3494#define CAN_F2R1_FB29_Pos (29U)
3495#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3496#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3497#define CAN_F2R1_FB30_Pos (30U)
3498#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3499#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3500#define CAN_F2R1_FB31_Pos (31U)
3501#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3502#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3504/******************* Bit definition for CAN_F3R1 register *******************/
3505#define CAN_F3R1_FB0_Pos (0U)
3506#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3507#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3508#define CAN_F3R1_FB1_Pos (1U)
3509#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3510#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3511#define CAN_F3R1_FB2_Pos (2U)
3512#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3513#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3514#define CAN_F3R1_FB3_Pos (3U)
3515#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3516#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3517#define CAN_F3R1_FB4_Pos (4U)
3518#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3519#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3520#define CAN_F3R1_FB5_Pos (5U)
3521#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3522#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3523#define CAN_F3R1_FB6_Pos (6U)
3524#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3525#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3526#define CAN_F3R1_FB7_Pos (7U)
3527#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3528#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3529#define CAN_F3R1_FB8_Pos (8U)
3530#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3531#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3532#define CAN_F3R1_FB9_Pos (9U)
3533#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3534#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3535#define CAN_F3R1_FB10_Pos (10U)
3536#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3537#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3538#define CAN_F3R1_FB11_Pos (11U)
3539#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3540#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3541#define CAN_F3R1_FB12_Pos (12U)
3542#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3543#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3544#define CAN_F3R1_FB13_Pos (13U)
3545#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3546#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3547#define CAN_F3R1_FB14_Pos (14U)
3548#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3549#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3550#define CAN_F3R1_FB15_Pos (15U)
3551#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3552#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3553#define CAN_F3R1_FB16_Pos (16U)
3554#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3555#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3556#define CAN_F3R1_FB17_Pos (17U)
3557#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3558#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3559#define CAN_F3R1_FB18_Pos (18U)
3560#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3561#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3562#define CAN_F3R1_FB19_Pos (19U)
3563#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3564#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3565#define CAN_F3R1_FB20_Pos (20U)
3566#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3567#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3568#define CAN_F3R1_FB21_Pos (21U)
3569#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3570#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3571#define CAN_F3R1_FB22_Pos (22U)
3572#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3573#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3574#define CAN_F3R1_FB23_Pos (23U)
3575#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3576#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3577#define CAN_F3R1_FB24_Pos (24U)
3578#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3579#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3580#define CAN_F3R1_FB25_Pos (25U)
3581#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3582#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3583#define CAN_F3R1_FB26_Pos (26U)
3584#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3585#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3586#define CAN_F3R1_FB27_Pos (27U)
3587#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3588#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3589#define CAN_F3R1_FB28_Pos (28U)
3590#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3591#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3592#define CAN_F3R1_FB29_Pos (29U)
3593#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3594#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3595#define CAN_F3R1_FB30_Pos (30U)
3596#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3597#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3598#define CAN_F3R1_FB31_Pos (31U)
3599#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3600#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3602/******************* Bit definition for CAN_F4R1 register *******************/
3603#define CAN_F4R1_FB0_Pos (0U)
3604#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3605#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3606#define CAN_F4R1_FB1_Pos (1U)
3607#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3608#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3609#define CAN_F4R1_FB2_Pos (2U)
3610#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3611#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3612#define CAN_F4R1_FB3_Pos (3U)
3613#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3614#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3615#define CAN_F4R1_FB4_Pos (4U)
3616#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3617#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3618#define CAN_F4R1_FB5_Pos (5U)
3619#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3620#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3621#define CAN_F4R1_FB6_Pos (6U)
3622#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3623#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3624#define CAN_F4R1_FB7_Pos (7U)
3625#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3626#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3627#define CAN_F4R1_FB8_Pos (8U)
3628#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3629#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3630#define CAN_F4R1_FB9_Pos (9U)
3631#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3632#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3633#define CAN_F4R1_FB10_Pos (10U)
3634#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3635#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3636#define CAN_F4R1_FB11_Pos (11U)
3637#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3638#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3639#define CAN_F4R1_FB12_Pos (12U)
3640#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3641#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3642#define CAN_F4R1_FB13_Pos (13U)
3643#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3644#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3645#define CAN_F4R1_FB14_Pos (14U)
3646#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3647#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3648#define CAN_F4R1_FB15_Pos (15U)
3649#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3650#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3651#define CAN_F4R1_FB16_Pos (16U)
3652#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3653#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3654#define CAN_F4R1_FB17_Pos (17U)
3655#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3656#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3657#define CAN_F4R1_FB18_Pos (18U)
3658#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3659#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3660#define CAN_F4R1_FB19_Pos (19U)
3661#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3662#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3663#define CAN_F4R1_FB20_Pos (20U)
3664#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3665#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3666#define CAN_F4R1_FB21_Pos (21U)
3667#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3668#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3669#define CAN_F4R1_FB22_Pos (22U)
3670#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3671#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3672#define CAN_F4R1_FB23_Pos (23U)
3673#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3674#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3675#define CAN_F4R1_FB24_Pos (24U)
3676#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3677#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3678#define CAN_F4R1_FB25_Pos (25U)
3679#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3680#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3681#define CAN_F4R1_FB26_Pos (26U)
3682#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3683#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3684#define CAN_F4R1_FB27_Pos (27U)
3685#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3686#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3687#define CAN_F4R1_FB28_Pos (28U)
3688#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3689#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3690#define CAN_F4R1_FB29_Pos (29U)
3691#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3692#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3693#define CAN_F4R1_FB30_Pos (30U)
3694#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3695#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3696#define CAN_F4R1_FB31_Pos (31U)
3697#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3698#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3700/******************* Bit definition for CAN_F5R1 register *******************/
3701#define CAN_F5R1_FB0_Pos (0U)
3702#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3703#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3704#define CAN_F5R1_FB1_Pos (1U)
3705#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3706#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3707#define CAN_F5R1_FB2_Pos (2U)
3708#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3709#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3710#define CAN_F5R1_FB3_Pos (3U)
3711#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3712#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3713#define CAN_F5R1_FB4_Pos (4U)
3714#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3715#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3716#define CAN_F5R1_FB5_Pos (5U)
3717#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3718#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3719#define CAN_F5R1_FB6_Pos (6U)
3720#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3721#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3722#define CAN_F5R1_FB7_Pos (7U)
3723#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3724#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3725#define CAN_F5R1_FB8_Pos (8U)
3726#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3727#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3728#define CAN_F5R1_FB9_Pos (9U)
3729#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3730#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3731#define CAN_F5R1_FB10_Pos (10U)
3732#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3733#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3734#define CAN_F5R1_FB11_Pos (11U)
3735#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3736#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3737#define CAN_F5R1_FB12_Pos (12U)
3738#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3739#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3740#define CAN_F5R1_FB13_Pos (13U)
3741#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3742#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3743#define CAN_F5R1_FB14_Pos (14U)
3744#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3745#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3746#define CAN_F5R1_FB15_Pos (15U)
3747#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3748#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3749#define CAN_F5R1_FB16_Pos (16U)
3750#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3751#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3752#define CAN_F5R1_FB17_Pos (17U)
3753#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3754#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3755#define CAN_F5R1_FB18_Pos (18U)
3756#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3757#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3758#define CAN_F5R1_FB19_Pos (19U)
3759#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3760#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3761#define CAN_F5R1_FB20_Pos (20U)
3762#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3763#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3764#define CAN_F5R1_FB21_Pos (21U)
3765#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3766#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3767#define CAN_F5R1_FB22_Pos (22U)
3768#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3769#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3770#define CAN_F5R1_FB23_Pos (23U)
3771#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3772#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3773#define CAN_F5R1_FB24_Pos (24U)
3774#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3775#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3776#define CAN_F5R1_FB25_Pos (25U)
3777#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3778#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3779#define CAN_F5R1_FB26_Pos (26U)
3780#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3781#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3782#define CAN_F5R1_FB27_Pos (27U)
3783#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3784#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3785#define CAN_F5R1_FB28_Pos (28U)
3786#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3787#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3788#define CAN_F5R1_FB29_Pos (29U)
3789#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3790#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3791#define CAN_F5R1_FB30_Pos (30U)
3792#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3793#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3794#define CAN_F5R1_FB31_Pos (31U)
3795#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3796#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3798/******************* Bit definition for CAN_F6R1 register *******************/
3799#define CAN_F6R1_FB0_Pos (0U)
3800#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3801#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3802#define CAN_F6R1_FB1_Pos (1U)
3803#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3804#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3805#define CAN_F6R1_FB2_Pos (2U)
3806#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3807#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3808#define CAN_F6R1_FB3_Pos (3U)
3809#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3810#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3811#define CAN_F6R1_FB4_Pos (4U)
3812#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3813#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3814#define CAN_F6R1_FB5_Pos (5U)
3815#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3816#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3817#define CAN_F6R1_FB6_Pos (6U)
3818#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3819#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3820#define CAN_F6R1_FB7_Pos (7U)
3821#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3822#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3823#define CAN_F6R1_FB8_Pos (8U)
3824#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3825#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3826#define CAN_F6R1_FB9_Pos (9U)
3827#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3828#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3829#define CAN_F6R1_FB10_Pos (10U)
3830#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3831#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3832#define CAN_F6R1_FB11_Pos (11U)
3833#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3834#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3835#define CAN_F6R1_FB12_Pos (12U)
3836#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3837#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3838#define CAN_F6R1_FB13_Pos (13U)
3839#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3840#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3841#define CAN_F6R1_FB14_Pos (14U)
3842#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3843#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3844#define CAN_F6R1_FB15_Pos (15U)
3845#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3846#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3847#define CAN_F6R1_FB16_Pos (16U)
3848#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3849#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3850#define CAN_F6R1_FB17_Pos (17U)
3851#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3852#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3853#define CAN_F6R1_FB18_Pos (18U)
3854#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3855#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3856#define CAN_F6R1_FB19_Pos (19U)
3857#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3858#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3859#define CAN_F6R1_FB20_Pos (20U)
3860#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3861#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3862#define CAN_F6R1_FB21_Pos (21U)
3863#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3864#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3865#define CAN_F6R1_FB22_Pos (22U)
3866#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3867#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3868#define CAN_F6R1_FB23_Pos (23U)
3869#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3870#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3871#define CAN_F6R1_FB24_Pos (24U)
3872#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3873#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3874#define CAN_F6R1_FB25_Pos (25U)
3875#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3876#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3877#define CAN_F6R1_FB26_Pos (26U)
3878#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3879#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3880#define CAN_F6R1_FB27_Pos (27U)
3881#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3882#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3883#define CAN_F6R1_FB28_Pos (28U)
3884#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3885#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3886#define CAN_F6R1_FB29_Pos (29U)
3887#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3888#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3889#define CAN_F6R1_FB30_Pos (30U)
3890#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3891#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3892#define CAN_F6R1_FB31_Pos (31U)
3893#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3894#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3896/******************* Bit definition for CAN_F7R1 register *******************/
3897#define CAN_F7R1_FB0_Pos (0U)
3898#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3899#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3900#define CAN_F7R1_FB1_Pos (1U)
3901#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3902#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3903#define CAN_F7R1_FB2_Pos (2U)
3904#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3905#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3906#define CAN_F7R1_FB3_Pos (3U)
3907#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3908#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3909#define CAN_F7R1_FB4_Pos (4U)
3910#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3911#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3912#define CAN_F7R1_FB5_Pos (5U)
3913#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3914#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3915#define CAN_F7R1_FB6_Pos (6U)
3916#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3917#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3918#define CAN_F7R1_FB7_Pos (7U)
3919#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3920#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3921#define CAN_F7R1_FB8_Pos (8U)
3922#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3923#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3924#define CAN_F7R1_FB9_Pos (9U)
3925#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3926#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3927#define CAN_F7R1_FB10_Pos (10U)
3928#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3929#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3930#define CAN_F7R1_FB11_Pos (11U)
3931#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3932#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3933#define CAN_F7R1_FB12_Pos (12U)
3934#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3935#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3936#define CAN_F7R1_FB13_Pos (13U)
3937#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3938#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3939#define CAN_F7R1_FB14_Pos (14U)
3940#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3941#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3942#define CAN_F7R1_FB15_Pos (15U)
3943#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3944#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3945#define CAN_F7R1_FB16_Pos (16U)
3946#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3947#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3948#define CAN_F7R1_FB17_Pos (17U)
3949#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3950#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3951#define CAN_F7R1_FB18_Pos (18U)
3952#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3953#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3954#define CAN_F7R1_FB19_Pos (19U)
3955#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3956#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3957#define CAN_F7R1_FB20_Pos (20U)
3958#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3959#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3960#define CAN_F7R1_FB21_Pos (21U)
3961#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3962#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3963#define CAN_F7R1_FB22_Pos (22U)
3964#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3965#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3966#define CAN_F7R1_FB23_Pos (23U)
3967#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3968#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3969#define CAN_F7R1_FB24_Pos (24U)
3970#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3971#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3972#define CAN_F7R1_FB25_Pos (25U)
3973#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3974#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3975#define CAN_F7R1_FB26_Pos (26U)
3976#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3977#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3978#define CAN_F7R1_FB27_Pos (27U)
3979#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3980#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3981#define CAN_F7R1_FB28_Pos (28U)
3982#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3983#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3984#define CAN_F7R1_FB29_Pos (29U)
3985#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3986#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3987#define CAN_F7R1_FB30_Pos (30U)
3988#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3989#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3990#define CAN_F7R1_FB31_Pos (31U)
3991#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3992#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3994/******************* Bit definition for CAN_F8R1 register *******************/
3995#define CAN_F8R1_FB0_Pos (0U)
3996#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3997#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3998#define CAN_F8R1_FB1_Pos (1U)
3999#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
4000#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
4001#define CAN_F8R1_FB2_Pos (2U)
4002#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
4003#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
4004#define CAN_F8R1_FB3_Pos (3U)
4005#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
4006#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
4007#define CAN_F8R1_FB4_Pos (4U)
4008#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
4009#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
4010#define CAN_F8R1_FB5_Pos (5U)
4011#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
4012#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
4013#define CAN_F8R1_FB6_Pos (6U)
4014#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
4015#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
4016#define CAN_F8R1_FB7_Pos (7U)
4017#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
4018#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
4019#define CAN_F8R1_FB8_Pos (8U)
4020#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
4021#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
4022#define CAN_F8R1_FB9_Pos (9U)
4023#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
4024#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
4025#define CAN_F8R1_FB10_Pos (10U)
4026#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
4027#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
4028#define CAN_F8R1_FB11_Pos (11U)
4029#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
4030#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
4031#define CAN_F8R1_FB12_Pos (12U)
4032#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
4033#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
4034#define CAN_F8R1_FB13_Pos (13U)
4035#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
4036#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
4037#define CAN_F8R1_FB14_Pos (14U)
4038#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
4039#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
4040#define CAN_F8R1_FB15_Pos (15U)
4041#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
4042#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
4043#define CAN_F8R1_FB16_Pos (16U)
4044#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
4045#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
4046#define CAN_F8R1_FB17_Pos (17U)
4047#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
4048#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
4049#define CAN_F8R1_FB18_Pos (18U)
4050#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
4051#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
4052#define CAN_F8R1_FB19_Pos (19U)
4053#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
4054#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
4055#define CAN_F8R1_FB20_Pos (20U)
4056#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
4057#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
4058#define CAN_F8R1_FB21_Pos (21U)
4059#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
4060#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
4061#define CAN_F8R1_FB22_Pos (22U)
4062#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
4063#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
4064#define CAN_F8R1_FB23_Pos (23U)
4065#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
4066#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
4067#define CAN_F8R1_FB24_Pos (24U)
4068#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
4069#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
4070#define CAN_F8R1_FB25_Pos (25U)
4071#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
4072#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
4073#define CAN_F8R1_FB26_Pos (26U)
4074#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
4075#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
4076#define CAN_F8R1_FB27_Pos (27U)
4077#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
4078#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
4079#define CAN_F8R1_FB28_Pos (28U)
4080#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
4081#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
4082#define CAN_F8R1_FB29_Pos (29U)
4083#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
4084#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
4085#define CAN_F8R1_FB30_Pos (30U)
4086#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
4087#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
4088#define CAN_F8R1_FB31_Pos (31U)
4089#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
4090#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
4092/******************* Bit definition for CAN_F9R1 register *******************/
4093#define CAN_F9R1_FB0_Pos (0U)
4094#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
4095#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
4096#define CAN_F9R1_FB1_Pos (1U)
4097#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
4098#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
4099#define CAN_F9R1_FB2_Pos (2U)
4100#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
4101#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
4102#define CAN_F9R1_FB3_Pos (3U)
4103#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
4104#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
4105#define CAN_F9R1_FB4_Pos (4U)
4106#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
4107#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
4108#define CAN_F9R1_FB5_Pos (5U)
4109#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
4110#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
4111#define CAN_F9R1_FB6_Pos (6U)
4112#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
4113#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
4114#define CAN_F9R1_FB7_Pos (7U)
4115#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
4116#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
4117#define CAN_F9R1_FB8_Pos (8U)
4118#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
4119#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
4120#define CAN_F9R1_FB9_Pos (9U)
4121#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
4122#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
4123#define CAN_F9R1_FB10_Pos (10U)
4124#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
4125#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
4126#define CAN_F9R1_FB11_Pos (11U)
4127#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
4128#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
4129#define CAN_F9R1_FB12_Pos (12U)
4130#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
4131#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
4132#define CAN_F9R1_FB13_Pos (13U)
4133#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
4134#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
4135#define CAN_F9R1_FB14_Pos (14U)
4136#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
4137#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
4138#define CAN_F9R1_FB15_Pos (15U)
4139#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
4140#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
4141#define CAN_F9R1_FB16_Pos (16U)
4142#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
4143#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
4144#define CAN_F9R1_FB17_Pos (17U)
4145#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
4146#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
4147#define CAN_F9R1_FB18_Pos (18U)
4148#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
4149#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
4150#define CAN_F9R1_FB19_Pos (19U)
4151#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
4152#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
4153#define CAN_F9R1_FB20_Pos (20U)
4154#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
4155#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
4156#define CAN_F9R1_FB21_Pos (21U)
4157#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
4158#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
4159#define CAN_F9R1_FB22_Pos (22U)
4160#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
4161#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
4162#define CAN_F9R1_FB23_Pos (23U)
4163#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
4164#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
4165#define CAN_F9R1_FB24_Pos (24U)
4166#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
4167#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
4168#define CAN_F9R1_FB25_Pos (25U)
4169#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
4170#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
4171#define CAN_F9R1_FB26_Pos (26U)
4172#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
4173#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
4174#define CAN_F9R1_FB27_Pos (27U)
4175#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
4176#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
4177#define CAN_F9R1_FB28_Pos (28U)
4178#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
4179#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
4180#define CAN_F9R1_FB29_Pos (29U)
4181#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
4182#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
4183#define CAN_F9R1_FB30_Pos (30U)
4184#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
4185#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
4186#define CAN_F9R1_FB31_Pos (31U)
4187#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
4188#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
4190/******************* Bit definition for CAN_F10R1 register ******************/
4191#define CAN_F10R1_FB0_Pos (0U)
4192#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
4193#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
4194#define CAN_F10R1_FB1_Pos (1U)
4195#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
4196#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
4197#define CAN_F10R1_FB2_Pos (2U)
4198#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
4199#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
4200#define CAN_F10R1_FB3_Pos (3U)
4201#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
4202#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
4203#define CAN_F10R1_FB4_Pos (4U)
4204#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
4205#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
4206#define CAN_F10R1_FB5_Pos (5U)
4207#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
4208#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
4209#define CAN_F10R1_FB6_Pos (6U)
4210#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
4211#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
4212#define CAN_F10R1_FB7_Pos (7U)
4213#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
4214#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
4215#define CAN_F10R1_FB8_Pos (8U)
4216#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
4217#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
4218#define CAN_F10R1_FB9_Pos (9U)
4219#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
4220#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
4221#define CAN_F10R1_FB10_Pos (10U)
4222#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
4223#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
4224#define CAN_F10R1_FB11_Pos (11U)
4225#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
4226#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
4227#define CAN_F10R1_FB12_Pos (12U)
4228#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
4229#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
4230#define CAN_F10R1_FB13_Pos (13U)
4231#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
4232#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
4233#define CAN_F10R1_FB14_Pos (14U)
4234#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
4235#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
4236#define CAN_F10R1_FB15_Pos (15U)
4237#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
4238#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
4239#define CAN_F10R1_FB16_Pos (16U)
4240#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
4241#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
4242#define CAN_F10R1_FB17_Pos (17U)
4243#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
4244#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
4245#define CAN_F10R1_FB18_Pos (18U)
4246#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
4247#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
4248#define CAN_F10R1_FB19_Pos (19U)
4249#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
4250#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
4251#define CAN_F10R1_FB20_Pos (20U)
4252#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
4253#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
4254#define CAN_F10R1_FB21_Pos (21U)
4255#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
4256#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
4257#define CAN_F10R1_FB22_Pos (22U)
4258#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
4259#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
4260#define CAN_F10R1_FB23_Pos (23U)
4261#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
4262#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
4263#define CAN_F10R1_FB24_Pos (24U)
4264#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
4265#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
4266#define CAN_F10R1_FB25_Pos (25U)
4267#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
4268#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
4269#define CAN_F10R1_FB26_Pos (26U)
4270#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
4271#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
4272#define CAN_F10R1_FB27_Pos (27U)
4273#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
4274#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
4275#define CAN_F10R1_FB28_Pos (28U)
4276#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
4277#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
4278#define CAN_F10R1_FB29_Pos (29U)
4279#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
4280#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
4281#define CAN_F10R1_FB30_Pos (30U)
4282#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
4283#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
4284#define CAN_F10R1_FB31_Pos (31U)
4285#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
4286#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
4288/******************* Bit definition for CAN_F11R1 register ******************/
4289#define CAN_F11R1_FB0_Pos (0U)
4290#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
4291#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
4292#define CAN_F11R1_FB1_Pos (1U)
4293#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
4294#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
4295#define CAN_F11R1_FB2_Pos (2U)
4296#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
4297#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
4298#define CAN_F11R1_FB3_Pos (3U)
4299#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
4300#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
4301#define CAN_F11R1_FB4_Pos (4U)
4302#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
4303#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
4304#define CAN_F11R1_FB5_Pos (5U)
4305#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
4306#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4307#define CAN_F11R1_FB6_Pos (6U)
4308#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4309#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4310#define CAN_F11R1_FB7_Pos (7U)
4311#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4312#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4313#define CAN_F11R1_FB8_Pos (8U)
4314#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4315#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4316#define CAN_F11R1_FB9_Pos (9U)
4317#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4318#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4319#define CAN_F11R1_FB10_Pos (10U)
4320#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4321#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4322#define CAN_F11R1_FB11_Pos (11U)
4323#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4324#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4325#define CAN_F11R1_FB12_Pos (12U)
4326#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4327#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4328#define CAN_F11R1_FB13_Pos (13U)
4329#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4330#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4331#define CAN_F11R1_FB14_Pos (14U)
4332#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4333#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4334#define CAN_F11R1_FB15_Pos (15U)
4335#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4336#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4337#define CAN_F11R1_FB16_Pos (16U)
4338#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4339#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4340#define CAN_F11R1_FB17_Pos (17U)
4341#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4342#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4343#define CAN_F11R1_FB18_Pos (18U)
4344#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4345#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4346#define CAN_F11R1_FB19_Pos (19U)
4347#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4348#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4349#define CAN_F11R1_FB20_Pos (20U)
4350#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4351#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4352#define CAN_F11R1_FB21_Pos (21U)
4353#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4354#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4355#define CAN_F11R1_FB22_Pos (22U)
4356#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4357#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4358#define CAN_F11R1_FB23_Pos (23U)
4359#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4360#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4361#define CAN_F11R1_FB24_Pos (24U)
4362#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4363#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4364#define CAN_F11R1_FB25_Pos (25U)
4365#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4366#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4367#define CAN_F11R1_FB26_Pos (26U)
4368#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4369#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4370#define CAN_F11R1_FB27_Pos (27U)
4371#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4372#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4373#define CAN_F11R1_FB28_Pos (28U)
4374#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4375#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4376#define CAN_F11R1_FB29_Pos (29U)
4377#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4378#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4379#define CAN_F11R1_FB30_Pos (30U)
4380#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4381#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4382#define CAN_F11R1_FB31_Pos (31U)
4383#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4384#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4386/******************* Bit definition for CAN_F12R1 register ******************/
4387#define CAN_F12R1_FB0_Pos (0U)
4388#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4389#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4390#define CAN_F12R1_FB1_Pos (1U)
4391#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4392#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4393#define CAN_F12R1_FB2_Pos (2U)
4394#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4395#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4396#define CAN_F12R1_FB3_Pos (3U)
4397#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4398#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4399#define CAN_F12R1_FB4_Pos (4U)
4400#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4401#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4402#define CAN_F12R1_FB5_Pos (5U)
4403#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4404#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4405#define CAN_F12R1_FB6_Pos (6U)
4406#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4407#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4408#define CAN_F12R1_FB7_Pos (7U)
4409#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4410#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4411#define CAN_F12R1_FB8_Pos (8U)
4412#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4413#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4414#define CAN_F12R1_FB9_Pos (9U)
4415#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4416#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4417#define CAN_F12R1_FB10_Pos (10U)
4418#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4419#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4420#define CAN_F12R1_FB11_Pos (11U)
4421#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4422#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4423#define CAN_F12R1_FB12_Pos (12U)
4424#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4425#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4426#define CAN_F12R1_FB13_Pos (13U)
4427#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4428#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4429#define CAN_F12R1_FB14_Pos (14U)
4430#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4431#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4432#define CAN_F12R1_FB15_Pos (15U)
4433#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4434#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4435#define CAN_F12R1_FB16_Pos (16U)
4436#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4437#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4438#define CAN_F12R1_FB17_Pos (17U)
4439#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4440#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4441#define CAN_F12R1_FB18_Pos (18U)
4442#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4443#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4444#define CAN_F12R1_FB19_Pos (19U)
4445#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4446#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4447#define CAN_F12R1_FB20_Pos (20U)
4448#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4449#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4450#define CAN_F12R1_FB21_Pos (21U)
4451#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4452#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4453#define CAN_F12R1_FB22_Pos (22U)
4454#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4455#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4456#define CAN_F12R1_FB23_Pos (23U)
4457#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4458#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4459#define CAN_F12R1_FB24_Pos (24U)
4460#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4461#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4462#define CAN_F12R1_FB25_Pos (25U)
4463#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4464#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4465#define CAN_F12R1_FB26_Pos (26U)
4466#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4467#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4468#define CAN_F12R1_FB27_Pos (27U)
4469#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4470#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4471#define CAN_F12R1_FB28_Pos (28U)
4472#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4473#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4474#define CAN_F12R1_FB29_Pos (29U)
4475#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4476#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4477#define CAN_F12R1_FB30_Pos (30U)
4478#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4479#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4480#define CAN_F12R1_FB31_Pos (31U)
4481#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4482#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4484/******************* Bit definition for CAN_F13R1 register ******************/
4485#define CAN_F13R1_FB0_Pos (0U)
4486#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4487#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4488#define CAN_F13R1_FB1_Pos (1U)
4489#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4490#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4491#define CAN_F13R1_FB2_Pos (2U)
4492#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4493#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4494#define CAN_F13R1_FB3_Pos (3U)
4495#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4496#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4497#define CAN_F13R1_FB4_Pos (4U)
4498#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4499#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4500#define CAN_F13R1_FB5_Pos (5U)
4501#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4502#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4503#define CAN_F13R1_FB6_Pos (6U)
4504#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4505#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4506#define CAN_F13R1_FB7_Pos (7U)
4507#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4508#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4509#define CAN_F13R1_FB8_Pos (8U)
4510#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4511#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4512#define CAN_F13R1_FB9_Pos (9U)
4513#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4514#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4515#define CAN_F13R1_FB10_Pos (10U)
4516#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4517#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4518#define CAN_F13R1_FB11_Pos (11U)
4519#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4520#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4521#define CAN_F13R1_FB12_Pos (12U)
4522#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4523#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4524#define CAN_F13R1_FB13_Pos (13U)
4525#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4526#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4527#define CAN_F13R1_FB14_Pos (14U)
4528#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4529#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4530#define CAN_F13R1_FB15_Pos (15U)
4531#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4532#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4533#define CAN_F13R1_FB16_Pos (16U)
4534#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4535#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4536#define CAN_F13R1_FB17_Pos (17U)
4537#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4538#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4539#define CAN_F13R1_FB18_Pos (18U)
4540#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4541#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4542#define CAN_F13R1_FB19_Pos (19U)
4543#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4544#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4545#define CAN_F13R1_FB20_Pos (20U)
4546#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4547#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4548#define CAN_F13R1_FB21_Pos (21U)
4549#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4550#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4551#define CAN_F13R1_FB22_Pos (22U)
4552#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4553#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4554#define CAN_F13R1_FB23_Pos (23U)
4555#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4556#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4557#define CAN_F13R1_FB24_Pos (24U)
4558#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4559#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4560#define CAN_F13R1_FB25_Pos (25U)
4561#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4562#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4563#define CAN_F13R1_FB26_Pos (26U)
4564#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4565#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4566#define CAN_F13R1_FB27_Pos (27U)
4567#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4568#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4569#define CAN_F13R1_FB28_Pos (28U)
4570#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4571#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4572#define CAN_F13R1_FB29_Pos (29U)
4573#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4574#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4575#define CAN_F13R1_FB30_Pos (30U)
4576#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4577#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4578#define CAN_F13R1_FB31_Pos (31U)
4579#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4580#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4582/******************* Bit definition for CAN_F0R2 register *******************/
4583#define CAN_F0R2_FB0_Pos (0U)
4584#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4585#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4586#define CAN_F0R2_FB1_Pos (1U)
4587#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4588#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4589#define CAN_F0R2_FB2_Pos (2U)
4590#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4591#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4592#define CAN_F0R2_FB3_Pos (3U)
4593#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4594#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4595#define CAN_F0R2_FB4_Pos (4U)
4596#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4597#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4598#define CAN_F0R2_FB5_Pos (5U)
4599#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4600#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4601#define CAN_F0R2_FB6_Pos (6U)
4602#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4603#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4604#define CAN_F0R2_FB7_Pos (7U)
4605#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4606#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4607#define CAN_F0R2_FB8_Pos (8U)
4608#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4609#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4610#define CAN_F0R2_FB9_Pos (9U)
4611#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4612#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4613#define CAN_F0R2_FB10_Pos (10U)
4614#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4615#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4616#define CAN_F0R2_FB11_Pos (11U)
4617#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4618#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4619#define CAN_F0R2_FB12_Pos (12U)
4620#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4621#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4622#define CAN_F0R2_FB13_Pos (13U)
4623#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4624#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4625#define CAN_F0R2_FB14_Pos (14U)
4626#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4627#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4628#define CAN_F0R2_FB15_Pos (15U)
4629#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4630#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4631#define CAN_F0R2_FB16_Pos (16U)
4632#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4633#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4634#define CAN_F0R2_FB17_Pos (17U)
4635#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4636#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4637#define CAN_F0R2_FB18_Pos (18U)
4638#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4639#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4640#define CAN_F0R2_FB19_Pos (19U)
4641#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4642#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4643#define CAN_F0R2_FB20_Pos (20U)
4644#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4645#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4646#define CAN_F0R2_FB21_Pos (21U)
4647#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4648#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4649#define CAN_F0R2_FB22_Pos (22U)
4650#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4651#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4652#define CAN_F0R2_FB23_Pos (23U)
4653#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4654#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4655#define CAN_F0R2_FB24_Pos (24U)
4656#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4657#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4658#define CAN_F0R2_FB25_Pos (25U)
4659#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4660#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4661#define CAN_F0R2_FB26_Pos (26U)
4662#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4663#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4664#define CAN_F0R2_FB27_Pos (27U)
4665#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4666#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4667#define CAN_F0R2_FB28_Pos (28U)
4668#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4669#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4670#define CAN_F0R2_FB29_Pos (29U)
4671#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4672#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4673#define CAN_F0R2_FB30_Pos (30U)
4674#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4675#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4676#define CAN_F0R2_FB31_Pos (31U)
4677#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4678#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4680/******************* Bit definition for CAN_F1R2 register *******************/
4681#define CAN_F1R2_FB0_Pos (0U)
4682#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4683#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4684#define CAN_F1R2_FB1_Pos (1U)
4685#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4686#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4687#define CAN_F1R2_FB2_Pos (2U)
4688#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4689#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4690#define CAN_F1R2_FB3_Pos (3U)
4691#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4692#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4693#define CAN_F1R2_FB4_Pos (4U)
4694#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4695#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4696#define CAN_F1R2_FB5_Pos (5U)
4697#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4698#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4699#define CAN_F1R2_FB6_Pos (6U)
4700#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4701#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4702#define CAN_F1R2_FB7_Pos (7U)
4703#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4704#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4705#define CAN_F1R2_FB8_Pos (8U)
4706#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4707#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4708#define CAN_F1R2_FB9_Pos (9U)
4709#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4710#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4711#define CAN_F1R2_FB10_Pos (10U)
4712#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4713#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4714#define CAN_F1R2_FB11_Pos (11U)
4715#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4716#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4717#define CAN_F1R2_FB12_Pos (12U)
4718#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4719#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4720#define CAN_F1R2_FB13_Pos (13U)
4721#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4722#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4723#define CAN_F1R2_FB14_Pos (14U)
4724#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4725#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4726#define CAN_F1R2_FB15_Pos (15U)
4727#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4728#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4729#define CAN_F1R2_FB16_Pos (16U)
4730#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4731#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4732#define CAN_F1R2_FB17_Pos (17U)
4733#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4734#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4735#define CAN_F1R2_FB18_Pos (18U)
4736#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4737#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4738#define CAN_F1R2_FB19_Pos (19U)
4739#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4740#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4741#define CAN_F1R2_FB20_Pos (20U)
4742#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4743#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4744#define CAN_F1R2_FB21_Pos (21U)
4745#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4746#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4747#define CAN_F1R2_FB22_Pos (22U)
4748#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4749#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4750#define CAN_F1R2_FB23_Pos (23U)
4751#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4752#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4753#define CAN_F1R2_FB24_Pos (24U)
4754#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4755#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4756#define CAN_F1R2_FB25_Pos (25U)
4757#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4758#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4759#define CAN_F1R2_FB26_Pos (26U)
4760#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4761#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4762#define CAN_F1R2_FB27_Pos (27U)
4763#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4764#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4765#define CAN_F1R2_FB28_Pos (28U)
4766#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4767#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4768#define CAN_F1R2_FB29_Pos (29U)
4769#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4770#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4771#define CAN_F1R2_FB30_Pos (30U)
4772#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4773#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4774#define CAN_F1R2_FB31_Pos (31U)
4775#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4776#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4778/******************* Bit definition for CAN_F2R2 register *******************/
4779#define CAN_F2R2_FB0_Pos (0U)
4780#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4781#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4782#define CAN_F2R2_FB1_Pos (1U)
4783#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4784#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4785#define CAN_F2R2_FB2_Pos (2U)
4786#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4787#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4788#define CAN_F2R2_FB3_Pos (3U)
4789#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4790#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4791#define CAN_F2R2_FB4_Pos (4U)
4792#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4793#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4794#define CAN_F2R2_FB5_Pos (5U)
4795#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4796#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4797#define CAN_F2R2_FB6_Pos (6U)
4798#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4799#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4800#define CAN_F2R2_FB7_Pos (7U)
4801#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4802#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4803#define CAN_F2R2_FB8_Pos (8U)
4804#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4805#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4806#define CAN_F2R2_FB9_Pos (9U)
4807#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4808#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4809#define CAN_F2R2_FB10_Pos (10U)
4810#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4811#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4812#define CAN_F2R2_FB11_Pos (11U)
4813#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4814#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4815#define CAN_F2R2_FB12_Pos (12U)
4816#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4817#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4818#define CAN_F2R2_FB13_Pos (13U)
4819#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4820#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4821#define CAN_F2R2_FB14_Pos (14U)
4822#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4823#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4824#define CAN_F2R2_FB15_Pos (15U)
4825#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4826#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4827#define CAN_F2R2_FB16_Pos (16U)
4828#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4829#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4830#define CAN_F2R2_FB17_Pos (17U)
4831#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4832#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4833#define CAN_F2R2_FB18_Pos (18U)
4834#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4835#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4836#define CAN_F2R2_FB19_Pos (19U)
4837#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4838#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4839#define CAN_F2R2_FB20_Pos (20U)
4840#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4841#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4842#define CAN_F2R2_FB21_Pos (21U)
4843#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4844#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4845#define CAN_F2R2_FB22_Pos (22U)
4846#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4847#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4848#define CAN_F2R2_FB23_Pos (23U)
4849#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4850#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4851#define CAN_F2R2_FB24_Pos (24U)
4852#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4853#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4854#define CAN_F2R2_FB25_Pos (25U)
4855#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4856#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4857#define CAN_F2R2_FB26_Pos (26U)
4858#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4859#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4860#define CAN_F2R2_FB27_Pos (27U)
4861#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4862#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4863#define CAN_F2R2_FB28_Pos (28U)
4864#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4865#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4866#define CAN_F2R2_FB29_Pos (29U)
4867#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4868#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4869#define CAN_F2R2_FB30_Pos (30U)
4870#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4871#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4872#define CAN_F2R2_FB31_Pos (31U)
4873#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4874#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4876/******************* Bit definition for CAN_F3R2 register *******************/
4877#define CAN_F3R2_FB0_Pos (0U)
4878#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4879#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4880#define CAN_F3R2_FB1_Pos (1U)
4881#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4882#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4883#define CAN_F3R2_FB2_Pos (2U)
4884#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4885#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4886#define CAN_F3R2_FB3_Pos (3U)
4887#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4888#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4889#define CAN_F3R2_FB4_Pos (4U)
4890#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4891#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4892#define CAN_F3R2_FB5_Pos (5U)
4893#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4894#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4895#define CAN_F3R2_FB6_Pos (6U)
4896#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4897#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4898#define CAN_F3R2_FB7_Pos (7U)
4899#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4900#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4901#define CAN_F3R2_FB8_Pos (8U)
4902#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4903#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4904#define CAN_F3R2_FB9_Pos (9U)
4905#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4906#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4907#define CAN_F3R2_FB10_Pos (10U)
4908#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4909#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4910#define CAN_F3R2_FB11_Pos (11U)
4911#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4912#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4913#define CAN_F3R2_FB12_Pos (12U)
4914#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4915#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4916#define CAN_F3R2_FB13_Pos (13U)
4917#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4918#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4919#define CAN_F3R2_FB14_Pos (14U)
4920#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4921#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4922#define CAN_F3R2_FB15_Pos (15U)
4923#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4924#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4925#define CAN_F3R2_FB16_Pos (16U)
4926#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4927#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4928#define CAN_F3R2_FB17_Pos (17U)
4929#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4930#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4931#define CAN_F3R2_FB18_Pos (18U)
4932#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4933#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4934#define CAN_F3R2_FB19_Pos (19U)
4935#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4936#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4937#define CAN_F3R2_FB20_Pos (20U)
4938#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4939#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4940#define CAN_F3R2_FB21_Pos (21U)
4941#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4942#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4943#define CAN_F3R2_FB22_Pos (22U)
4944#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4945#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4946#define CAN_F3R2_FB23_Pos (23U)
4947#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4948#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4949#define CAN_F3R2_FB24_Pos (24U)
4950#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4951#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4952#define CAN_F3R2_FB25_Pos (25U)
4953#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4954#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4955#define CAN_F3R2_FB26_Pos (26U)
4956#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4957#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4958#define CAN_F3R2_FB27_Pos (27U)
4959#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4960#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4961#define CAN_F3R2_FB28_Pos (28U)
4962#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4963#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4964#define CAN_F3R2_FB29_Pos (29U)
4965#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4966#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4967#define CAN_F3R2_FB30_Pos (30U)
4968#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4969#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4970#define CAN_F3R2_FB31_Pos (31U)
4971#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4972#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4974/******************* Bit definition for CAN_F4R2 register *******************/
4975#define CAN_F4R2_FB0_Pos (0U)
4976#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4977#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4978#define CAN_F4R2_FB1_Pos (1U)
4979#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4980#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4981#define CAN_F4R2_FB2_Pos (2U)
4982#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4983#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4984#define CAN_F4R2_FB3_Pos (3U)
4985#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4986#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4987#define CAN_F4R2_FB4_Pos (4U)
4988#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4989#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4990#define CAN_F4R2_FB5_Pos (5U)
4991#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4992#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4993#define CAN_F4R2_FB6_Pos (6U)
4994#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4995#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4996#define CAN_F4R2_FB7_Pos (7U)
4997#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4998#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4999#define CAN_F4R2_FB8_Pos (8U)
5000#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
5001#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
5002#define CAN_F4R2_FB9_Pos (9U)
5003#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
5004#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
5005#define CAN_F4R2_FB10_Pos (10U)
5006#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
5007#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
5008#define CAN_F4R2_FB11_Pos (11U)
5009#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
5010#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
5011#define CAN_F4R2_FB12_Pos (12U)
5012#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
5013#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
5014#define CAN_F4R2_FB13_Pos (13U)
5015#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
5016#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
5017#define CAN_F4R2_FB14_Pos (14U)
5018#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
5019#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
5020#define CAN_F4R2_FB15_Pos (15U)
5021#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
5022#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
5023#define CAN_F4R2_FB16_Pos (16U)
5024#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
5025#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
5026#define CAN_F4R2_FB17_Pos (17U)
5027#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
5028#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
5029#define CAN_F4R2_FB18_Pos (18U)
5030#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
5031#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
5032#define CAN_F4R2_FB19_Pos (19U)
5033#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
5034#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
5035#define CAN_F4R2_FB20_Pos (20U)
5036#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
5037#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
5038#define CAN_F4R2_FB21_Pos (21U)
5039#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
5040#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
5041#define CAN_F4R2_FB22_Pos (22U)
5042#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
5043#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
5044#define CAN_F4R2_FB23_Pos (23U)
5045#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
5046#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
5047#define CAN_F4R2_FB24_Pos (24U)
5048#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
5049#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
5050#define CAN_F4R2_FB25_Pos (25U)
5051#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
5052#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
5053#define CAN_F4R2_FB26_Pos (26U)
5054#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
5055#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
5056#define CAN_F4R2_FB27_Pos (27U)
5057#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
5058#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
5059#define CAN_F4R2_FB28_Pos (28U)
5060#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
5061#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
5062#define CAN_F4R2_FB29_Pos (29U)
5063#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
5064#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
5065#define CAN_F4R2_FB30_Pos (30U)
5066#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
5067#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
5068#define CAN_F4R2_FB31_Pos (31U)
5069#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
5070#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
5072/******************* Bit definition for CAN_F5R2 register *******************/
5073#define CAN_F5R2_FB0_Pos (0U)
5074#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
5075#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
5076#define CAN_F5R2_FB1_Pos (1U)
5077#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
5078#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
5079#define CAN_F5R2_FB2_Pos (2U)
5080#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
5081#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
5082#define CAN_F5R2_FB3_Pos (3U)
5083#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
5084#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
5085#define CAN_F5R2_FB4_Pos (4U)
5086#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
5087#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
5088#define CAN_F5R2_FB5_Pos (5U)
5089#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
5090#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
5091#define CAN_F5R2_FB6_Pos (6U)
5092#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
5093#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
5094#define CAN_F5R2_FB7_Pos (7U)
5095#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
5096#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
5097#define CAN_F5R2_FB8_Pos (8U)
5098#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
5099#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
5100#define CAN_F5R2_FB9_Pos (9U)
5101#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
5102#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
5103#define CAN_F5R2_FB10_Pos (10U)
5104#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
5105#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
5106#define CAN_F5R2_FB11_Pos (11U)
5107#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
5108#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
5109#define CAN_F5R2_FB12_Pos (12U)
5110#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
5111#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
5112#define CAN_F5R2_FB13_Pos (13U)
5113#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
5114#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
5115#define CAN_F5R2_FB14_Pos (14U)
5116#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
5117#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
5118#define CAN_F5R2_FB15_Pos (15U)
5119#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
5120#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
5121#define CAN_F5R2_FB16_Pos (16U)
5122#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
5123#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
5124#define CAN_F5R2_FB17_Pos (17U)
5125#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
5126#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
5127#define CAN_F5R2_FB18_Pos (18U)
5128#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
5129#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
5130#define CAN_F5R2_FB19_Pos (19U)
5131#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
5132#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
5133#define CAN_F5R2_FB20_Pos (20U)
5134#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
5135#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
5136#define CAN_F5R2_FB21_Pos (21U)
5137#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
5138#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
5139#define CAN_F5R2_FB22_Pos (22U)
5140#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
5141#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
5142#define CAN_F5R2_FB23_Pos (23U)
5143#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
5144#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
5145#define CAN_F5R2_FB24_Pos (24U)
5146#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
5147#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
5148#define CAN_F5R2_FB25_Pos (25U)
5149#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
5150#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
5151#define CAN_F5R2_FB26_Pos (26U)
5152#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
5153#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
5154#define CAN_F5R2_FB27_Pos (27U)
5155#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
5156#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
5157#define CAN_F5R2_FB28_Pos (28U)
5158#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
5159#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
5160#define CAN_F5R2_FB29_Pos (29U)
5161#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
5162#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
5163#define CAN_F5R2_FB30_Pos (30U)
5164#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
5165#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
5166#define CAN_F5R2_FB31_Pos (31U)
5167#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
5168#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
5170/******************* Bit definition for CAN_F6R2 register *******************/
5171#define CAN_F6R2_FB0_Pos (0U)
5172#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
5173#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
5174#define CAN_F6R2_FB1_Pos (1U)
5175#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
5176#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
5177#define CAN_F6R2_FB2_Pos (2U)
5178#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
5179#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
5180#define CAN_F6R2_FB3_Pos (3U)
5181#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
5182#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
5183#define CAN_F6R2_FB4_Pos (4U)
5184#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
5185#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
5186#define CAN_F6R2_FB5_Pos (5U)
5187#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
5188#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
5189#define CAN_F6R2_FB6_Pos (6U)
5190#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
5191#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
5192#define CAN_F6R2_FB7_Pos (7U)
5193#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
5194#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
5195#define CAN_F6R2_FB8_Pos (8U)
5196#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
5197#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
5198#define CAN_F6R2_FB9_Pos (9U)
5199#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
5200#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
5201#define CAN_F6R2_FB10_Pos (10U)
5202#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
5203#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
5204#define CAN_F6R2_FB11_Pos (11U)
5205#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
5206#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
5207#define CAN_F6R2_FB12_Pos (12U)
5208#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
5209#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
5210#define CAN_F6R2_FB13_Pos (13U)
5211#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
5212#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
5213#define CAN_F6R2_FB14_Pos (14U)
5214#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
5215#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
5216#define CAN_F6R2_FB15_Pos (15U)
5217#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
5218#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
5219#define CAN_F6R2_FB16_Pos (16U)
5220#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
5221#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
5222#define CAN_F6R2_FB17_Pos (17U)
5223#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
5224#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
5225#define CAN_F6R2_FB18_Pos (18U)
5226#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
5227#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
5228#define CAN_F6R2_FB19_Pos (19U)
5229#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
5230#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
5231#define CAN_F6R2_FB20_Pos (20U)
5232#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
5233#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
5234#define CAN_F6R2_FB21_Pos (21U)
5235#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
5236#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
5237#define CAN_F6R2_FB22_Pos (22U)
5238#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
5239#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
5240#define CAN_F6R2_FB23_Pos (23U)
5241#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
5242#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
5243#define CAN_F6R2_FB24_Pos (24U)
5244#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
5245#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
5246#define CAN_F6R2_FB25_Pos (25U)
5247#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
5248#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
5249#define CAN_F6R2_FB26_Pos (26U)
5250#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
5251#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
5252#define CAN_F6R2_FB27_Pos (27U)
5253#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
5254#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
5255#define CAN_F6R2_FB28_Pos (28U)
5256#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
5257#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
5258#define CAN_F6R2_FB29_Pos (29U)
5259#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
5260#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
5261#define CAN_F6R2_FB30_Pos (30U)
5262#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
5263#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
5264#define CAN_F6R2_FB31_Pos (31U)
5265#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
5266#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
5268/******************* Bit definition for CAN_F7R2 register *******************/
5269#define CAN_F7R2_FB0_Pos (0U)
5270#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
5271#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
5272#define CAN_F7R2_FB1_Pos (1U)
5273#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
5274#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
5275#define CAN_F7R2_FB2_Pos (2U)
5276#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
5277#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
5278#define CAN_F7R2_FB3_Pos (3U)
5279#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
5280#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
5281#define CAN_F7R2_FB4_Pos (4U)
5282#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
5283#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
5284#define CAN_F7R2_FB5_Pos (5U)
5285#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
5286#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
5287#define CAN_F7R2_FB6_Pos (6U)
5288#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
5289#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
5290#define CAN_F7R2_FB7_Pos (7U)
5291#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
5292#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
5293#define CAN_F7R2_FB8_Pos (8U)
5294#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
5295#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
5296#define CAN_F7R2_FB9_Pos (9U)
5297#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
5298#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
5299#define CAN_F7R2_FB10_Pos (10U)
5300#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
5301#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
5302#define CAN_F7R2_FB11_Pos (11U)
5303#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
5304#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
5305#define CAN_F7R2_FB12_Pos (12U)
5306#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5307#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5308#define CAN_F7R2_FB13_Pos (13U)
5309#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5310#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5311#define CAN_F7R2_FB14_Pos (14U)
5312#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5313#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5314#define CAN_F7R2_FB15_Pos (15U)
5315#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5316#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5317#define CAN_F7R2_FB16_Pos (16U)
5318#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5319#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5320#define CAN_F7R2_FB17_Pos (17U)
5321#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5322#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5323#define CAN_F7R2_FB18_Pos (18U)
5324#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5325#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5326#define CAN_F7R2_FB19_Pos (19U)
5327#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5328#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5329#define CAN_F7R2_FB20_Pos (20U)
5330#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5331#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5332#define CAN_F7R2_FB21_Pos (21U)
5333#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5334#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5335#define CAN_F7R2_FB22_Pos (22U)
5336#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5337#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5338#define CAN_F7R2_FB23_Pos (23U)
5339#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5340#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5341#define CAN_F7R2_FB24_Pos (24U)
5342#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5343#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5344#define CAN_F7R2_FB25_Pos (25U)
5345#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5346#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5347#define CAN_F7R2_FB26_Pos (26U)
5348#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5349#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5350#define CAN_F7R2_FB27_Pos (27U)
5351#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5352#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5353#define CAN_F7R2_FB28_Pos (28U)
5354#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5355#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5356#define CAN_F7R2_FB29_Pos (29U)
5357#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5358#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5359#define CAN_F7R2_FB30_Pos (30U)
5360#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5361#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5362#define CAN_F7R2_FB31_Pos (31U)
5363#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5364#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5366/******************* Bit definition for CAN_F8R2 register *******************/
5367#define CAN_F8R2_FB0_Pos (0U)
5368#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5369#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5370#define CAN_F8R2_FB1_Pos (1U)
5371#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5372#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5373#define CAN_F8R2_FB2_Pos (2U)
5374#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5375#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5376#define CAN_F8R2_FB3_Pos (3U)
5377#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5378#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5379#define CAN_F8R2_FB4_Pos (4U)
5380#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5381#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5382#define CAN_F8R2_FB5_Pos (5U)
5383#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5384#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5385#define CAN_F8R2_FB6_Pos (6U)
5386#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5387#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5388#define CAN_F8R2_FB7_Pos (7U)
5389#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5390#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5391#define CAN_F8R2_FB8_Pos (8U)
5392#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5393#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5394#define CAN_F8R2_FB9_Pos (9U)
5395#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5396#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5397#define CAN_F8R2_FB10_Pos (10U)
5398#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5399#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5400#define CAN_F8R2_FB11_Pos (11U)
5401#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5402#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5403#define CAN_F8R2_FB12_Pos (12U)
5404#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5405#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5406#define CAN_F8R2_FB13_Pos (13U)
5407#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5408#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5409#define CAN_F8R2_FB14_Pos (14U)
5410#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5411#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5412#define CAN_F8R2_FB15_Pos (15U)
5413#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5414#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5415#define CAN_F8R2_FB16_Pos (16U)
5416#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5417#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5418#define CAN_F8R2_FB17_Pos (17U)
5419#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5420#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5421#define CAN_F8R2_FB18_Pos (18U)
5422#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5423#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5424#define CAN_F8R2_FB19_Pos (19U)
5425#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5426#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5427#define CAN_F8R2_FB20_Pos (20U)
5428#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5429#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5430#define CAN_F8R2_FB21_Pos (21U)
5431#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5432#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5433#define CAN_F8R2_FB22_Pos (22U)
5434#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5435#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5436#define CAN_F8R2_FB23_Pos (23U)
5437#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5438#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5439#define CAN_F8R2_FB24_Pos (24U)
5440#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5441#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5442#define CAN_F8R2_FB25_Pos (25U)
5443#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5444#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5445#define CAN_F8R2_FB26_Pos (26U)
5446#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5447#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5448#define CAN_F8R2_FB27_Pos (27U)
5449#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5450#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5451#define CAN_F8R2_FB28_Pos (28U)
5452#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5453#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5454#define CAN_F8R2_FB29_Pos (29U)
5455#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5456#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5457#define CAN_F8R2_FB30_Pos (30U)
5458#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5459#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5460#define CAN_F8R2_FB31_Pos (31U)
5461#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5462#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5464/******************* Bit definition for CAN_F9R2 register *******************/
5465#define CAN_F9R2_FB0_Pos (0U)
5466#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5467#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5468#define CAN_F9R2_FB1_Pos (1U)
5469#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5470#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5471#define CAN_F9R2_FB2_Pos (2U)
5472#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5473#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5474#define CAN_F9R2_FB3_Pos (3U)
5475#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5476#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5477#define CAN_F9R2_FB4_Pos (4U)
5478#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5479#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5480#define CAN_F9R2_FB5_Pos (5U)
5481#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5482#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5483#define CAN_F9R2_FB6_Pos (6U)
5484#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5485#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5486#define CAN_F9R2_FB7_Pos (7U)
5487#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5488#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5489#define CAN_F9R2_FB8_Pos (8U)
5490#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5491#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5492#define CAN_F9R2_FB9_Pos (9U)
5493#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5494#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5495#define CAN_F9R2_FB10_Pos (10U)
5496#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5497#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5498#define CAN_F9R2_FB11_Pos (11U)
5499#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5500#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5501#define CAN_F9R2_FB12_Pos (12U)
5502#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5503#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5504#define CAN_F9R2_FB13_Pos (13U)
5505#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5506#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5507#define CAN_F9R2_FB14_Pos (14U)
5508#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5509#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5510#define CAN_F9R2_FB15_Pos (15U)
5511#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5512#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5513#define CAN_F9R2_FB16_Pos (16U)
5514#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5515#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5516#define CAN_F9R2_FB17_Pos (17U)
5517#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5518#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5519#define CAN_F9R2_FB18_Pos (18U)
5520#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5521#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5522#define CAN_F9R2_FB19_Pos (19U)
5523#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5524#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5525#define CAN_F9R2_FB20_Pos (20U)
5526#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5527#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5528#define CAN_F9R2_FB21_Pos (21U)
5529#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5530#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5531#define CAN_F9R2_FB22_Pos (22U)
5532#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5533#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5534#define CAN_F9R2_FB23_Pos (23U)
5535#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5536#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5537#define CAN_F9R2_FB24_Pos (24U)
5538#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5539#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5540#define CAN_F9R2_FB25_Pos (25U)
5541#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5542#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5543#define CAN_F9R2_FB26_Pos (26U)
5544#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5545#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5546#define CAN_F9R2_FB27_Pos (27U)
5547#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5548#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5549#define CAN_F9R2_FB28_Pos (28U)
5550#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5551#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5552#define CAN_F9R2_FB29_Pos (29U)
5553#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5554#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5555#define CAN_F9R2_FB30_Pos (30U)
5556#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5557#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5558#define CAN_F9R2_FB31_Pos (31U)
5559#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5560#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5562/******************* Bit definition for CAN_F10R2 register ******************/
5563#define CAN_F10R2_FB0_Pos (0U)
5564#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5565#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5566#define CAN_F10R2_FB1_Pos (1U)
5567#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5568#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5569#define CAN_F10R2_FB2_Pos (2U)
5570#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5571#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5572#define CAN_F10R2_FB3_Pos (3U)
5573#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5574#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5575#define CAN_F10R2_FB4_Pos (4U)
5576#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5577#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5578#define CAN_F10R2_FB5_Pos (5U)
5579#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5580#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5581#define CAN_F10R2_FB6_Pos (6U)
5582#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5583#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5584#define CAN_F10R2_FB7_Pos (7U)
5585#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5586#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5587#define CAN_F10R2_FB8_Pos (8U)
5588#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5589#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5590#define CAN_F10R2_FB9_Pos (9U)
5591#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5592#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5593#define CAN_F10R2_FB10_Pos (10U)
5594#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5595#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5596#define CAN_F10R2_FB11_Pos (11U)
5597#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5598#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5599#define CAN_F10R2_FB12_Pos (12U)
5600#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5601#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5602#define CAN_F10R2_FB13_Pos (13U)
5603#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5604#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5605#define CAN_F10R2_FB14_Pos (14U)
5606#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5607#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5608#define CAN_F10R2_FB15_Pos (15U)
5609#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5610#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5611#define CAN_F10R2_FB16_Pos (16U)
5612#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5613#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5614#define CAN_F10R2_FB17_Pos (17U)
5615#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5616#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5617#define CAN_F10R2_FB18_Pos (18U)
5618#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5619#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5620#define CAN_F10R2_FB19_Pos (19U)
5621#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5622#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5623#define CAN_F10R2_FB20_Pos (20U)
5624#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5625#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5626#define CAN_F10R2_FB21_Pos (21U)
5627#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5628#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5629#define CAN_F10R2_FB22_Pos (22U)
5630#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5631#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5632#define CAN_F10R2_FB23_Pos (23U)
5633#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5634#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5635#define CAN_F10R2_FB24_Pos (24U)
5636#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5637#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5638#define CAN_F10R2_FB25_Pos (25U)
5639#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5640#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5641#define CAN_F10R2_FB26_Pos (26U)
5642#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5643#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5644#define CAN_F10R2_FB27_Pos (27U)
5645#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5646#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5647#define CAN_F10R2_FB28_Pos (28U)
5648#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5649#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5650#define CAN_F10R2_FB29_Pos (29U)
5651#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5652#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5653#define CAN_F10R2_FB30_Pos (30U)
5654#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5655#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5656#define CAN_F10R2_FB31_Pos (31U)
5657#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5658#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5660/******************* Bit definition for CAN_F11R2 register ******************/
5661#define CAN_F11R2_FB0_Pos (0U)
5662#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5663#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5664#define CAN_F11R2_FB1_Pos (1U)
5665#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5666#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5667#define CAN_F11R2_FB2_Pos (2U)
5668#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5669#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5670#define CAN_F11R2_FB3_Pos (3U)
5671#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5672#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5673#define CAN_F11R2_FB4_Pos (4U)
5674#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5675#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5676#define CAN_F11R2_FB5_Pos (5U)
5677#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5678#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5679#define CAN_F11R2_FB6_Pos (6U)
5680#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5681#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5682#define CAN_F11R2_FB7_Pos (7U)
5683#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5684#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5685#define CAN_F11R2_FB8_Pos (8U)
5686#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5687#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5688#define CAN_F11R2_FB9_Pos (9U)
5689#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5690#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5691#define CAN_F11R2_FB10_Pos (10U)
5692#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5693#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5694#define CAN_F11R2_FB11_Pos (11U)
5695#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5696#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5697#define CAN_F11R2_FB12_Pos (12U)
5698#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5699#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5700#define CAN_F11R2_FB13_Pos (13U)
5701#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5702#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5703#define CAN_F11R2_FB14_Pos (14U)
5704#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5705#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5706#define CAN_F11R2_FB15_Pos (15U)
5707#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5708#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5709#define CAN_F11R2_FB16_Pos (16U)
5710#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5711#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5712#define CAN_F11R2_FB17_Pos (17U)
5713#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5714#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5715#define CAN_F11R2_FB18_Pos (18U)
5716#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5717#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5718#define CAN_F11R2_FB19_Pos (19U)
5719#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5720#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5721#define CAN_F11R2_FB20_Pos (20U)
5722#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5723#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5724#define CAN_F11R2_FB21_Pos (21U)
5725#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5726#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5727#define CAN_F11R2_FB22_Pos (22U)
5728#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5729#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5730#define CAN_F11R2_FB23_Pos (23U)
5731#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5732#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5733#define CAN_F11R2_FB24_Pos (24U)
5734#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5735#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5736#define CAN_F11R2_FB25_Pos (25U)
5737#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5738#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5739#define CAN_F11R2_FB26_Pos (26U)
5740#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5741#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5742#define CAN_F11R2_FB27_Pos (27U)
5743#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5744#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5745#define CAN_F11R2_FB28_Pos (28U)
5746#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5747#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5748#define CAN_F11R2_FB29_Pos (29U)
5749#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5750#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5751#define CAN_F11R2_FB30_Pos (30U)
5752#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5753#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5754#define CAN_F11R2_FB31_Pos (31U)
5755#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5756#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5758/******************* Bit definition for CAN_F12R2 register ******************/
5759#define CAN_F12R2_FB0_Pos (0U)
5760#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5761#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5762#define CAN_F12R2_FB1_Pos (1U)
5763#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5764#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5765#define CAN_F12R2_FB2_Pos (2U)
5766#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5767#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5768#define CAN_F12R2_FB3_Pos (3U)
5769#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5770#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5771#define CAN_F12R2_FB4_Pos (4U)
5772#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5773#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5774#define CAN_F12R2_FB5_Pos (5U)
5775#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5776#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5777#define CAN_F12R2_FB6_Pos (6U)
5778#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5779#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5780#define CAN_F12R2_FB7_Pos (7U)
5781#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5782#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5783#define CAN_F12R2_FB8_Pos (8U)
5784#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5785#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5786#define CAN_F12R2_FB9_Pos (9U)
5787#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5788#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5789#define CAN_F12R2_FB10_Pos (10U)
5790#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5791#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5792#define CAN_F12R2_FB11_Pos (11U)
5793#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5794#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5795#define CAN_F12R2_FB12_Pos (12U)
5796#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5797#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5798#define CAN_F12R2_FB13_Pos (13U)
5799#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5800#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5801#define CAN_F12R2_FB14_Pos (14U)
5802#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5803#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5804#define CAN_F12R2_FB15_Pos (15U)
5805#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5806#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5807#define CAN_F12R2_FB16_Pos (16U)
5808#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5809#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5810#define CAN_F12R2_FB17_Pos (17U)
5811#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5812#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5813#define CAN_F12R2_FB18_Pos (18U)
5814#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5815#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5816#define CAN_F12R2_FB19_Pos (19U)
5817#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5818#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5819#define CAN_F12R2_FB20_Pos (20U)
5820#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5821#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5822#define CAN_F12R2_FB21_Pos (21U)
5823#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5824#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5825#define CAN_F12R2_FB22_Pos (22U)
5826#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5827#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5828#define CAN_F12R2_FB23_Pos (23U)
5829#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5830#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5831#define CAN_F12R2_FB24_Pos (24U)
5832#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5833#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5834#define CAN_F12R2_FB25_Pos (25U)
5835#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5836#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5837#define CAN_F12R2_FB26_Pos (26U)
5838#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5839#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5840#define CAN_F12R2_FB27_Pos (27U)
5841#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5842#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5843#define CAN_F12R2_FB28_Pos (28U)
5844#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5845#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5846#define CAN_F12R2_FB29_Pos (29U)
5847#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5848#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5849#define CAN_F12R2_FB30_Pos (30U)
5850#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5851#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5852#define CAN_F12R2_FB31_Pos (31U)
5853#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5854#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5856/******************* Bit definition for CAN_F13R2 register ******************/
5857#define CAN_F13R2_FB0_Pos (0U)
5858#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5859#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5860#define CAN_F13R2_FB1_Pos (1U)
5861#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5862#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5863#define CAN_F13R2_FB2_Pos (2U)
5864#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5865#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5866#define CAN_F13R2_FB3_Pos (3U)
5867#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5868#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5869#define CAN_F13R2_FB4_Pos (4U)
5870#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5871#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5872#define CAN_F13R2_FB5_Pos (5U)
5873#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5874#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5875#define CAN_F13R2_FB6_Pos (6U)
5876#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5877#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5878#define CAN_F13R2_FB7_Pos (7U)
5879#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5880#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5881#define CAN_F13R2_FB8_Pos (8U)
5882#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5883#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5884#define CAN_F13R2_FB9_Pos (9U)
5885#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5886#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5887#define CAN_F13R2_FB10_Pos (10U)
5888#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5889#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5890#define CAN_F13R2_FB11_Pos (11U)
5891#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5892#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5893#define CAN_F13R2_FB12_Pos (12U)
5894#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5895#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5896#define CAN_F13R2_FB13_Pos (13U)
5897#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5898#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5899#define CAN_F13R2_FB14_Pos (14U)
5900#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5901#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5902#define CAN_F13R2_FB15_Pos (15U)
5903#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5904#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5905#define CAN_F13R2_FB16_Pos (16U)
5906#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5907#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5908#define CAN_F13R2_FB17_Pos (17U)
5909#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5910#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5911#define CAN_F13R2_FB18_Pos (18U)
5912#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5913#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5914#define CAN_F13R2_FB19_Pos (19U)
5915#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5916#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5917#define CAN_F13R2_FB20_Pos (20U)
5918#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5919#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5920#define CAN_F13R2_FB21_Pos (21U)
5921#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5922#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5923#define CAN_F13R2_FB22_Pos (22U)
5924#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5925#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5926#define CAN_F13R2_FB23_Pos (23U)
5927#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5928#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5929#define CAN_F13R2_FB24_Pos (24U)
5930#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5931#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5932#define CAN_F13R2_FB25_Pos (25U)
5933#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5934#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5935#define CAN_F13R2_FB26_Pos (26U)
5936#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5937#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5938#define CAN_F13R2_FB27_Pos (27U)
5939#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5940#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5941#define CAN_F13R2_FB28_Pos (28U)
5942#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5943#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5944#define CAN_F13R2_FB29_Pos (29U)
5945#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5946#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5947#define CAN_F13R2_FB30_Pos (30U)
5948#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5949#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5950#define CAN_F13R2_FB31_Pos (31U)
5951#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5952#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5954/******************************************************************************/
5955/* */
5956/* CRC calculation unit */
5957/* */
5958/******************************************************************************/
5959/******************* Bit definition for CRC_DR register *********************/
5960#define CRC_DR_DR_Pos (0U)
5961#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5962#define CRC_DR_DR CRC_DR_DR_Msk
5964/******************* Bit definition for CRC_IDR register ********************/
5965#define CRC_IDR_IDR_Pos (0U)
5966#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos)
5967#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5969/******************** Bit definition for CRC_CR register ********************/
5970#define CRC_CR_RESET_Pos (0U)
5971#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5972#define CRC_CR_RESET CRC_CR_RESET_Msk
5973#define CRC_CR_POLYSIZE_Pos (3U)
5974#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5975#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5976#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5977#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5978#define CRC_CR_REV_IN_Pos (5U)
5979#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5980#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5981#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5982#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5983#define CRC_CR_REV_OUT_Pos (7U)
5984#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5985#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5987/******************* Bit definition for CRC_INIT register *******************/
5988#define CRC_INIT_INIT_Pos (0U)
5989#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5990#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5992/******************* Bit definition for CRC_POL register ********************/
5993#define CRC_POL_POL_Pos (0U)
5994#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5995#define CRC_POL_POL CRC_POL_POL_Msk
5997/******************************************************************************/
5998/* */
5999/* Digital to Analog Converter */
6000/* */
6001/******************************************************************************/
6002/*
6003 * @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
6004 */
6005#define DAC_CHANNEL2_SUPPORT
6007/******************** Bit definition for DAC_CR register ********************/
6008#define DAC_CR_EN1_Pos (0U)
6009#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
6010#define DAC_CR_EN1 DAC_CR_EN1_Msk
6011#define DAC_CR_TEN1_Pos (2U)
6012#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
6013#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
6015#define DAC_CR_TSEL1_Pos (3U)
6016#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
6017#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
6018#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
6019#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
6020#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
6022#define DAC_CR_WAVE1_Pos (6U)
6023#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
6024#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
6025#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
6026#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
6028#define DAC_CR_MAMP1_Pos (8U)
6029#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
6030#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
6031#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
6032#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
6033#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
6034#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
6036#define DAC_CR_DMAEN1_Pos (12U)
6037#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
6038#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
6039#define DAC_CR_DMAUDRIE1_Pos (13U)
6040#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
6041#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
6042#define DAC_CR_CEN1_Pos (14U)
6043#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
6044#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
6046#define DAC_CR_EN2_Pos (16U)
6047#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
6048#define DAC_CR_EN2 DAC_CR_EN2_Msk
6049#define DAC_CR_TEN2_Pos (18U)
6050#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
6051#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
6053#define DAC_CR_TSEL2_Pos (19U)
6054#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
6055#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
6056#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
6057#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
6058#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
6060#define DAC_CR_WAVE2_Pos (22U)
6061#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
6062#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
6063#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
6064#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
6066#define DAC_CR_MAMP2_Pos (24U)
6067#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
6068#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
6069#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
6070#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
6071#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
6072#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
6074#define DAC_CR_DMAEN2_Pos (28U)
6075#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
6076#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
6077#define DAC_CR_DMAUDRIE2_Pos (29U)
6078#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
6079#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
6080#define DAC_CR_CEN2_Pos (30U)
6081#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
6082#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
6084/***************** Bit definition for DAC_SWTRIGR register ******************/
6085#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
6086#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
6087#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
6088#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
6089#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
6090#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
6092/***************** Bit definition for DAC_DHR12R1 register ******************/
6093#define DAC_DHR12R1_DACC1DHR_Pos (0U)
6094#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
6095#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
6097/***************** Bit definition for DAC_DHR12L1 register ******************/
6098#define DAC_DHR12L1_DACC1DHR_Pos (4U)
6099#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
6100#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
6102/****************** Bit definition for DAC_DHR8R1 register ******************/
6103#define DAC_DHR8R1_DACC1DHR_Pos (0U)
6104#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
6105#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
6107/***************** Bit definition for DAC_DHR12R2 register ******************/
6108#define DAC_DHR12R2_DACC2DHR_Pos (0U)
6109#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
6110#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
6112/***************** Bit definition for DAC_DHR12L2 register ******************/
6113#define DAC_DHR12L2_DACC2DHR_Pos (4U)
6114#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
6115#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
6117/****************** Bit definition for DAC_DHR8R2 register ******************/
6118#define DAC_DHR8R2_DACC2DHR_Pos (0U)
6119#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
6120#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
6122/***************** Bit definition for DAC_DHR12RD register ******************/
6123#define DAC_DHR12RD_DACC1DHR_Pos (0U)
6124#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
6125#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
6126#define DAC_DHR12RD_DACC2DHR_Pos (16U)
6127#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
6128#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
6130/***************** Bit definition for DAC_DHR12LD register ******************/
6131#define DAC_DHR12LD_DACC1DHR_Pos (4U)
6132#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
6133#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
6134#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6135#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6136#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6138/****************** Bit definition for DAC_DHR8RD register ******************/
6139#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6140#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6141#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6142#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6143#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6144#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6146/******************* Bit definition for DAC_DOR1 register *******************/
6147#define DAC_DOR1_DACC1DOR_Pos (0U)
6148#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6149#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6151/******************* Bit definition for DAC_DOR2 register *******************/
6152#define DAC_DOR2_DACC2DOR_Pos (0U)
6153#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6154#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6156/******************** Bit definition for DAC_SR register ********************/
6157#define DAC_SR_DMAUDR1_Pos (13U)
6158#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6159#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6160#define DAC_SR_CAL_FLAG1_Pos (14U)
6161#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
6162#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
6163#define DAC_SR_BWST1_Pos (15U)
6164#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos)
6165#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
6167#define DAC_SR_DMAUDR2_Pos (29U)
6168#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6169#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6170#define DAC_SR_CAL_FLAG2_Pos (30U)
6171#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
6172#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
6173#define DAC_SR_BWST2_Pos (31U)
6174#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
6175#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
6177/******************* Bit definition for DAC_CCR register ********************/
6178#define DAC_CCR_OTRIM1_Pos (0U)
6179#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
6180#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
6181#define DAC_CCR_OTRIM2_Pos (16U)
6182#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
6183#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
6185/******************* Bit definition for DAC_MCR register *******************/
6186#define DAC_MCR_MODE1_Pos (0U)
6187#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6188#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6189#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6190#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6191#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6193#define DAC_MCR_MODE2_Pos (16U)
6194#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6195#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6196#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6197#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6198#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6200/****************** Bit definition for DAC_SHSR1 register ******************/
6201#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6202#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6203#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6205/****************** Bit definition for DAC_SHSR2 register ******************/
6206#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6207#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6208#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6210/****************** Bit definition for DAC_SHHR register ******************/
6211#define DAC_SHHR_THOLD1_Pos (0U)
6212#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6213#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6214#define DAC_SHHR_THOLD2_Pos (16U)
6215#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6216#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6218/****************** Bit definition for DAC_SHRR register ******************/
6219#define DAC_SHRR_TREFRESH1_Pos (0U)
6220#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6221#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6222#define DAC_SHRR_TREFRESH2_Pos (16U)
6223#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6224#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6226/******************************************************************************/
6227/* */
6228/* Digital Filter for Sigma Delta Modulators */
6229/* */
6230/******************************************************************************/
6231
6232/**************** DFSDM channel configuration registers ********************/
6233
6234/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6235#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6236#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6237#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6238#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6239#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6240#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6241#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6242#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6243#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6244#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6245#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6246#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6247#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6248#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6249#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6250#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6251#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6252#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6253#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6254#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6255#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6256#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6257#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6258#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6259#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6260#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6261#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6262#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6263#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6264#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6265#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6266#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6267#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6268#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6269#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6270#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6271#define DFSDM_CHCFGR1_SITP_Pos (0U)
6272#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6273#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6274#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6275#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6277/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6278#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6279#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6280#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6281#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6282#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6283#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6285/**************** Bit definition for DFSDM_CHAWSCDR register *****************/
6286#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6287#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6288#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6289#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6290#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6291#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6292#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6293#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6294#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6295#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6296#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6297#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6298#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6299#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6301/**************** Bit definition for DFSDM_CHWDATR register *******************/
6302#define DFSDM_CHWDATR_WDATA_Pos (0U)
6303#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6304#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6306/**************** Bit definition for DFSDM_CHDATINR register *****************/
6307#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6308#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6309#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6310#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6311#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6312#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6314/************************ DFSDM module registers ****************************/
6315
6316/***************** Bit definition for DFSDM_FLTCR1 register *******************/
6317#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6318#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6319#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6320#define DFSDM_FLTCR1_FAST_Pos (29U)
6321#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6322#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6323#define DFSDM_FLTCR1_RCH_Pos (24U)
6324#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6325#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6326#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6327#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6328#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6329#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6330#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6331#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6332#define DFSDM_FLTCR1_RCONT_Pos (18U)
6333#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6334#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6335#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6336#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6337#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6338#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6339#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6340#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6341#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6342#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6343#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6344#define DFSDM_FLTCR1_JEXTSEL_Msk (0x7UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6345#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6346#define DFSDM_FLTCR1_JEXTSEL_2 (0x4UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6347#define DFSDM_FLTCR1_JEXTSEL_1 (0x2UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6348#define DFSDM_FLTCR1_JEXTSEL_0 (0x1UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6349#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6350#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6351#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6352#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6353#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6354#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6355#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6356#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6357#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6358#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6359#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6360#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6361#define DFSDM_FLTCR1_DFEN_Pos (0U)
6362#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6363#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6365/***************** Bit definition for DFSDM_FLTCR2 register *******************/
6366#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6367#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6368#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6369#define DFSDM_FLTCR2_EXCH_Pos (8U)
6370#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6371#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6372#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6373#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6374#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6375#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6376#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6377#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6378#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6379#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6380#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6381#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6382#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6383#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6384#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6385#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6386#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6387#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6388#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6389#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6390#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6391#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6392#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6394/***************** Bit definition for DFSDM_FLTISR register *******************/
6395#define DFSDM_FLTISR_SCDF_Pos (24U)
6396#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6397#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6398#define DFSDM_FLTISR_CKABF_Pos (16U)
6399#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6400#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6401#define DFSDM_FLTISR_RCIP_Pos (14U)
6402#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6403#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6404#define DFSDM_FLTISR_JCIP_Pos (13U)
6405#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6406#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6407#define DFSDM_FLTISR_AWDF_Pos (4U)
6408#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6409#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6410#define DFSDM_FLTISR_ROVRF_Pos (3U)
6411#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6412#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6413#define DFSDM_FLTISR_JOVRF_Pos (2U)
6414#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6415#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6416#define DFSDM_FLTISR_REOCF_Pos (1U)
6417#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6418#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6419#define DFSDM_FLTISR_JEOCF_Pos (0U)
6420#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6421#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6423/***************** Bit definition for DFSDM_FLTICR register *******************/
6424#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6425#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6426#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6427#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6428#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6429#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6430#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6431#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6432#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6433#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6434#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6435#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6437/**************** Bit definition for DFSDM_FLTJCHGR register ******************/
6438#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6439#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6440#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6442/***************** Bit definition for DFSDM_FLTFCR register *******************/
6443#define DFSDM_FLTFCR_FORD_Pos (29U)
6444#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6445#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6446#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6447#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6448#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6449#define DFSDM_FLTFCR_FOSR_Pos (16U)
6450#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6451#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6452#define DFSDM_FLTFCR_IOSR_Pos (0U)
6453#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6454#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6456/*************** Bit definition for DFSDM_FLTJDATAR register *****************/
6457#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6458#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6459#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6460#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6461#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6462#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6464/*************** Bit definition for DFSDM_FLTRDATAR register *****************/
6465#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6466#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6467#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6468#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6469#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6470#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6471#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6472#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6473#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6475/*************** Bit definition for DFSDM_FLTAWHTR register ******************/
6476#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6477#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6478#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6479#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6480#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6481#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6483/*************** Bit definition for DFSDM_FLTAWLTR register ******************/
6484#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6485#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6486#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6487#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6488#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6489#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6491/*************** Bit definition for DFSDM_FLTAWSR register *******************/
6492#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6493#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6494#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6495#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6496#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6497#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6499/*************** Bit definition for DFSDM_FLTAWCFR register ******************/
6500#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6501#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6502#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6503#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6504#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6505#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6507/*************** Bit definition for DFSDM_FLTEXMAX register ******************/
6508#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6509#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6510#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6511#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6512#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6513#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6515/*************** Bit definition for DFSDM_FLTEXMIN register ******************/
6516#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6517#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6518#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6519#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6520#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6521#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6523/*************** Bit definition for DFSDM_FLTCNVTIMR register ****************/
6524#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6525#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6526#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6528/******************************************************************************/
6529/* */
6530/* DMA Controller (DMA) */
6531/* */
6532/******************************************************************************/
6533
6534/******************* Bit definition for DMA_ISR register ********************/
6535#define DMA_ISR_GIF1_Pos (0U)
6536#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
6537#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
6538#define DMA_ISR_TCIF1_Pos (1U)
6539#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
6540#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
6541#define DMA_ISR_HTIF1_Pos (2U)
6542#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
6543#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
6544#define DMA_ISR_TEIF1_Pos (3U)
6545#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
6546#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
6547#define DMA_ISR_GIF2_Pos (4U)
6548#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
6549#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
6550#define DMA_ISR_TCIF2_Pos (5U)
6551#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
6552#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
6553#define DMA_ISR_HTIF2_Pos (6U)
6554#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
6555#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
6556#define DMA_ISR_TEIF2_Pos (7U)
6557#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
6558#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
6559#define DMA_ISR_GIF3_Pos (8U)
6560#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
6561#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
6562#define DMA_ISR_TCIF3_Pos (9U)
6563#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
6564#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
6565#define DMA_ISR_HTIF3_Pos (10U)
6566#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
6567#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
6568#define DMA_ISR_TEIF3_Pos (11U)
6569#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
6570#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
6571#define DMA_ISR_GIF4_Pos (12U)
6572#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
6573#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
6574#define DMA_ISR_TCIF4_Pos (13U)
6575#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
6576#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
6577#define DMA_ISR_HTIF4_Pos (14U)
6578#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
6579#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
6580#define DMA_ISR_TEIF4_Pos (15U)
6581#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
6582#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
6583#define DMA_ISR_GIF5_Pos (16U)
6584#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
6585#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
6586#define DMA_ISR_TCIF5_Pos (17U)
6587#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
6588#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
6589#define DMA_ISR_HTIF5_Pos (18U)
6590#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
6591#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
6592#define DMA_ISR_TEIF5_Pos (19U)
6593#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
6594#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
6595#define DMA_ISR_GIF6_Pos (20U)
6596#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
6597#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
6598#define DMA_ISR_TCIF6_Pos (21U)
6599#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
6600#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
6601#define DMA_ISR_HTIF6_Pos (22U)
6602#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
6603#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
6604#define DMA_ISR_TEIF6_Pos (23U)
6605#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
6606#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
6607#define DMA_ISR_GIF7_Pos (24U)
6608#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
6609#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
6610#define DMA_ISR_TCIF7_Pos (25U)
6611#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
6612#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
6613#define DMA_ISR_HTIF7_Pos (26U)
6614#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
6615#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
6616#define DMA_ISR_TEIF7_Pos (27U)
6617#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
6618#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
6620/******************* Bit definition for DMA_IFCR register *******************/
6621#define DMA_IFCR_CGIF1_Pos (0U)
6622#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
6623#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
6624#define DMA_IFCR_CTCIF1_Pos (1U)
6625#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
6626#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
6627#define DMA_IFCR_CHTIF1_Pos (2U)
6628#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
6629#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
6630#define DMA_IFCR_CTEIF1_Pos (3U)
6631#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
6632#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
6633#define DMA_IFCR_CGIF2_Pos (4U)
6634#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
6635#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
6636#define DMA_IFCR_CTCIF2_Pos (5U)
6637#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
6638#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
6639#define DMA_IFCR_CHTIF2_Pos (6U)
6640#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
6641#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
6642#define DMA_IFCR_CTEIF2_Pos (7U)
6643#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
6644#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
6645#define DMA_IFCR_CGIF3_Pos (8U)
6646#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
6647#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
6648#define DMA_IFCR_CTCIF3_Pos (9U)
6649#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
6650#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
6651#define DMA_IFCR_CHTIF3_Pos (10U)
6652#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
6653#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
6654#define DMA_IFCR_CTEIF3_Pos (11U)
6655#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
6656#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
6657#define DMA_IFCR_CGIF4_Pos (12U)
6658#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
6659#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
6660#define DMA_IFCR_CTCIF4_Pos (13U)
6661#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
6662#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
6663#define DMA_IFCR_CHTIF4_Pos (14U)
6664#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
6665#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
6666#define DMA_IFCR_CTEIF4_Pos (15U)
6667#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
6668#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
6669#define DMA_IFCR_CGIF5_Pos (16U)
6670#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
6671#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
6672#define DMA_IFCR_CTCIF5_Pos (17U)
6673#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
6674#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
6675#define DMA_IFCR_CHTIF5_Pos (18U)
6676#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
6677#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
6678#define DMA_IFCR_CTEIF5_Pos (19U)
6679#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
6680#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
6681#define DMA_IFCR_CGIF6_Pos (20U)
6682#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
6683#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
6684#define DMA_IFCR_CTCIF6_Pos (21U)
6685#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
6686#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
6687#define DMA_IFCR_CHTIF6_Pos (22U)
6688#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
6689#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
6690#define DMA_IFCR_CTEIF6_Pos (23U)
6691#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
6692#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
6693#define DMA_IFCR_CGIF7_Pos (24U)
6694#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
6695#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
6696#define DMA_IFCR_CTCIF7_Pos (25U)
6697#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
6698#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
6699#define DMA_IFCR_CHTIF7_Pos (26U)
6700#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
6701#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
6702#define DMA_IFCR_CTEIF7_Pos (27U)
6703#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
6704#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
6706/******************* Bit definition for DMA_CCR register ********************/
6707#define DMA_CCR_EN_Pos (0U)
6708#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
6709#define DMA_CCR_EN DMA_CCR_EN_Msk
6710#define DMA_CCR_TCIE_Pos (1U)
6711#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
6712#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
6713#define DMA_CCR_HTIE_Pos (2U)
6714#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
6715#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
6716#define DMA_CCR_TEIE_Pos (3U)
6717#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
6718#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
6719#define DMA_CCR_DIR_Pos (4U)
6720#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
6721#define DMA_CCR_DIR DMA_CCR_DIR_Msk
6722#define DMA_CCR_CIRC_Pos (5U)
6723#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
6724#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
6725#define DMA_CCR_PINC_Pos (6U)
6726#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
6727#define DMA_CCR_PINC DMA_CCR_PINC_Msk
6728#define DMA_CCR_MINC_Pos (7U)
6729#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
6730#define DMA_CCR_MINC DMA_CCR_MINC_Msk
6732#define DMA_CCR_PSIZE_Pos (8U)
6733#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
6734#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
6735#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
6736#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
6738#define DMA_CCR_MSIZE_Pos (10U)
6739#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
6740#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
6741#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
6742#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
6744#define DMA_CCR_PL_Pos (12U)
6745#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
6746#define DMA_CCR_PL DMA_CCR_PL_Msk
6747#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
6748#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
6750#define DMA_CCR_MEM2MEM_Pos (14U)
6751#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
6752#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
6754/****************** Bit definition for DMA_CNDTR register *******************/
6755#define DMA_CNDTR_NDT_Pos (0U)
6756#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
6757#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
6759/****************** Bit definition for DMA_CPAR register ********************/
6760#define DMA_CPAR_PA_Pos (0U)
6761#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
6762#define DMA_CPAR_PA DMA_CPAR_PA_Msk
6764/****************** Bit definition for DMA_CMAR register ********************/
6765#define DMA_CMAR_MA_Pos (0U)
6766#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
6767#define DMA_CMAR_MA DMA_CMAR_MA_Msk
6770/******************* Bit definition for DMA_CSELR register *******************/
6771#define DMA_CSELR_C1S_Pos (0U)
6772#define DMA_CSELR_C1S_Msk (0xFUL << DMA_CSELR_C1S_Pos)
6773#define DMA_CSELR_C1S DMA_CSELR_C1S_Msk
6774#define DMA_CSELR_C2S_Pos (4U)
6775#define DMA_CSELR_C2S_Msk (0xFUL << DMA_CSELR_C2S_Pos)
6776#define DMA_CSELR_C2S DMA_CSELR_C2S_Msk
6777#define DMA_CSELR_C3S_Pos (8U)
6778#define DMA_CSELR_C3S_Msk (0xFUL << DMA_CSELR_C3S_Pos)
6779#define DMA_CSELR_C3S DMA_CSELR_C3S_Msk
6780#define DMA_CSELR_C4S_Pos (12U)
6781#define DMA_CSELR_C4S_Msk (0xFUL << DMA_CSELR_C4S_Pos)
6782#define DMA_CSELR_C4S DMA_CSELR_C4S_Msk
6783#define DMA_CSELR_C5S_Pos (16U)
6784#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos)
6785#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk
6786#define DMA_CSELR_C6S_Pos (20U)
6787#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos)
6788#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk
6789#define DMA_CSELR_C7S_Pos (24U)
6790#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos)
6791#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk
6793/******************************************************************************/
6794/* */
6795/* External Interrupt/Event Controller */
6796/* */
6797/******************************************************************************/
6798/******************* Bit definition for EXTI_IMR1 register ******************/
6799#define EXTI_IMR1_IM0_Pos (0U)
6800#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
6801#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
6802#define EXTI_IMR1_IM1_Pos (1U)
6803#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
6804#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
6805#define EXTI_IMR1_IM2_Pos (2U)
6806#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
6807#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
6808#define EXTI_IMR1_IM3_Pos (3U)
6809#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
6810#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
6811#define EXTI_IMR1_IM4_Pos (4U)
6812#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
6813#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
6814#define EXTI_IMR1_IM5_Pos (5U)
6815#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
6816#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
6817#define EXTI_IMR1_IM6_Pos (6U)
6818#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
6819#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
6820#define EXTI_IMR1_IM7_Pos (7U)
6821#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
6822#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
6823#define EXTI_IMR1_IM8_Pos (8U)
6824#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
6825#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
6826#define EXTI_IMR1_IM9_Pos (9U)
6827#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
6828#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
6829#define EXTI_IMR1_IM10_Pos (10U)
6830#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
6831#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
6832#define EXTI_IMR1_IM11_Pos (11U)
6833#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
6834#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
6835#define EXTI_IMR1_IM12_Pos (12U)
6836#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
6837#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
6838#define EXTI_IMR1_IM13_Pos (13U)
6839#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
6840#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
6841#define EXTI_IMR1_IM14_Pos (14U)
6842#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
6843#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
6844#define EXTI_IMR1_IM15_Pos (15U)
6845#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
6846#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
6847#define EXTI_IMR1_IM16_Pos (16U)
6848#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
6849#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
6850#define EXTI_IMR1_IM17_Pos (17U)
6851#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
6852#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
6853#define EXTI_IMR1_IM18_Pos (18U)
6854#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
6855#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
6856#define EXTI_IMR1_IM19_Pos (19U)
6857#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
6858#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
6859#define EXTI_IMR1_IM20_Pos (20U)
6860#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
6861#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
6862#define EXTI_IMR1_IM21_Pos (21U)
6863#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
6864#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
6865#define EXTI_IMR1_IM22_Pos (22U)
6866#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
6867#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
6868#define EXTI_IMR1_IM23_Pos (23U)
6869#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
6870#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
6871#define EXTI_IMR1_IM24_Pos (24U)
6872#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
6873#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
6874#define EXTI_IMR1_IM25_Pos (25U)
6875#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
6876#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
6877#define EXTI_IMR1_IM26_Pos (26U)
6878#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
6879#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
6880#define EXTI_IMR1_IM27_Pos (27U)
6881#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
6882#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
6883#define EXTI_IMR1_IM28_Pos (28U)
6884#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
6885#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
6886#define EXTI_IMR1_IM29_Pos (29U)
6887#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
6888#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
6889#define EXTI_IMR1_IM30_Pos (30U)
6890#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
6891#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
6892#define EXTI_IMR1_IM31_Pos (31U)
6893#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
6894#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
6895#define EXTI_IMR1_IM_Pos (0U)
6896#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
6897#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
6899/******************* Bit definition for EXTI_EMR1 register ******************/
6900#define EXTI_EMR1_EM0_Pos (0U)
6901#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
6902#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
6903#define EXTI_EMR1_EM1_Pos (1U)
6904#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
6905#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
6906#define EXTI_EMR1_EM2_Pos (2U)
6907#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
6908#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
6909#define EXTI_EMR1_EM3_Pos (3U)
6910#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
6911#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
6912#define EXTI_EMR1_EM4_Pos (4U)
6913#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
6914#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
6915#define EXTI_EMR1_EM5_Pos (5U)
6916#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
6917#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
6918#define EXTI_EMR1_EM6_Pos (6U)
6919#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
6920#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
6921#define EXTI_EMR1_EM7_Pos (7U)
6922#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
6923#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
6924#define EXTI_EMR1_EM8_Pos (8U)
6925#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
6926#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
6927#define EXTI_EMR1_EM9_Pos (9U)
6928#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
6929#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
6930#define EXTI_EMR1_EM10_Pos (10U)
6931#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
6932#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
6933#define EXTI_EMR1_EM11_Pos (11U)
6934#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
6935#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
6936#define EXTI_EMR1_EM12_Pos (12U)
6937#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
6938#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
6939#define EXTI_EMR1_EM13_Pos (13U)
6940#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
6941#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
6942#define EXTI_EMR1_EM14_Pos (14U)
6943#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
6944#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
6945#define EXTI_EMR1_EM15_Pos (15U)
6946#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
6947#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
6948#define EXTI_EMR1_EM16_Pos (16U)
6949#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
6950#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
6951#define EXTI_EMR1_EM17_Pos (17U)
6952#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
6953#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
6954#define EXTI_EMR1_EM18_Pos (18U)
6955#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
6956#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
6957#define EXTI_EMR1_EM19_Pos (19U)
6958#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)
6959#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk
6960#define EXTI_EMR1_EM20_Pos (20U)
6961#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
6962#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
6963#define EXTI_EMR1_EM21_Pos (21U)
6964#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
6965#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
6966#define EXTI_EMR1_EM22_Pos (22U)
6967#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
6968#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
6969#define EXTI_EMR1_EM23_Pos (23U)
6970#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
6971#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
6972#define EXTI_EMR1_EM24_Pos (24U)
6973#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
6974#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
6975#define EXTI_EMR1_EM25_Pos (25U)
6976#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
6977#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
6978#define EXTI_EMR1_EM26_Pos (26U)
6979#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
6980#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
6981#define EXTI_EMR1_EM27_Pos (27U)
6982#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
6983#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
6984#define EXTI_EMR1_EM28_Pos (28U)
6985#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
6986#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
6987#define EXTI_EMR1_EM29_Pos (29U)
6988#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
6989#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
6990#define EXTI_EMR1_EM30_Pos (30U)
6991#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
6992#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
6993#define EXTI_EMR1_EM31_Pos (31U)
6994#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
6995#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
6997/****************** Bit definition for EXTI_RTSR1 register ******************/
6998#define EXTI_RTSR1_RT0_Pos (0U)
6999#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)
7000#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk
7001#define EXTI_RTSR1_RT1_Pos (1U)
7002#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)
7003#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk
7004#define EXTI_RTSR1_RT2_Pos (2U)
7005#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)
7006#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk
7007#define EXTI_RTSR1_RT3_Pos (3U)
7008#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)
7009#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk
7010#define EXTI_RTSR1_RT4_Pos (4U)
7011#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)
7012#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk
7013#define EXTI_RTSR1_RT5_Pos (5U)
7014#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)
7015#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk
7016#define EXTI_RTSR1_RT6_Pos (6U)
7017#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)
7018#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk
7019#define EXTI_RTSR1_RT7_Pos (7U)
7020#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)
7021#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk
7022#define EXTI_RTSR1_RT8_Pos (8U)
7023#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)
7024#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk
7025#define EXTI_RTSR1_RT9_Pos (9U)
7026#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)
7027#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk
7028#define EXTI_RTSR1_RT10_Pos (10U)
7029#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)
7030#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk
7031#define EXTI_RTSR1_RT11_Pos (11U)
7032#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)
7033#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk
7034#define EXTI_RTSR1_RT12_Pos (12U)
7035#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)
7036#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk
7037#define EXTI_RTSR1_RT13_Pos (13U)
7038#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)
7039#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk
7040#define EXTI_RTSR1_RT14_Pos (14U)
7041#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)
7042#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk
7043#define EXTI_RTSR1_RT15_Pos (15U)
7044#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)
7045#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk
7046#define EXTI_RTSR1_RT16_Pos (16U)
7047#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos)
7048#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk
7049#define EXTI_RTSR1_RT18_Pos (18U)
7050#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos)
7051#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk
7052#define EXTI_RTSR1_RT19_Pos (19U)
7053#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos)
7054#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk
7055#define EXTI_RTSR1_RT20_Pos (20U)
7056#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos)
7057#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk
7058#define EXTI_RTSR1_RT21_Pos (21U)
7059#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos)
7060#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk
7061#define EXTI_RTSR1_RT22_Pos (22U)
7062#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos)
7063#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk
7065/****************** Bit definition for EXTI_FTSR1 register ******************/
7066#define EXTI_FTSR1_FT0_Pos (0U)
7067#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)
7068#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk
7069#define EXTI_FTSR1_FT1_Pos (1U)
7070#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)
7071#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk
7072#define EXTI_FTSR1_FT2_Pos (2U)
7073#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)
7074#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk
7075#define EXTI_FTSR1_FT3_Pos (3U)
7076#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)
7077#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk
7078#define EXTI_FTSR1_FT4_Pos (4U)
7079#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)
7080#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk
7081#define EXTI_FTSR1_FT5_Pos (5U)
7082#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)
7083#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk
7084#define EXTI_FTSR1_FT6_Pos (6U)
7085#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)
7086#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk
7087#define EXTI_FTSR1_FT7_Pos (7U)
7088#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)
7089#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk
7090#define EXTI_FTSR1_FT8_Pos (8U)
7091#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)
7092#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk
7093#define EXTI_FTSR1_FT9_Pos (9U)
7094#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)
7095#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk
7096#define EXTI_FTSR1_FT10_Pos (10U)
7097#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)
7098#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk
7099#define EXTI_FTSR1_FT11_Pos (11U)
7100#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)
7101#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk
7102#define EXTI_FTSR1_FT12_Pos (12U)
7103#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)
7104#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk
7105#define EXTI_FTSR1_FT13_Pos (13U)
7106#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)
7107#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk
7108#define EXTI_FTSR1_FT14_Pos (14U)
7109#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)
7110#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk
7111#define EXTI_FTSR1_FT15_Pos (15U)
7112#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)
7113#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk
7114#define EXTI_FTSR1_FT16_Pos (16U)
7115#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos)
7116#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk
7117#define EXTI_FTSR1_FT18_Pos (18U)
7118#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos)
7119#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk
7120#define EXTI_FTSR1_FT19_Pos (19U)
7121#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos)
7122#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk
7123#define EXTI_FTSR1_FT20_Pos (20U)
7124#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos)
7125#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk
7126#define EXTI_FTSR1_FT21_Pos (21U)
7127#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos)
7128#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk
7129#define EXTI_FTSR1_FT22_Pos (22U)
7130#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos)
7131#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk
7133/****************** Bit definition for EXTI_SWIER1 register *****************/
7134#define EXTI_SWIER1_SWI0_Pos (0U)
7135#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)
7136#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk
7137#define EXTI_SWIER1_SWI1_Pos (1U)
7138#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)
7139#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk
7140#define EXTI_SWIER1_SWI2_Pos (2U)
7141#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)
7142#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk
7143#define EXTI_SWIER1_SWI3_Pos (3U)
7144#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)
7145#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk
7146#define EXTI_SWIER1_SWI4_Pos (4U)
7147#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)
7148#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk
7149#define EXTI_SWIER1_SWI5_Pos (5U)
7150#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)
7151#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk
7152#define EXTI_SWIER1_SWI6_Pos (6U)
7153#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)
7154#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk
7155#define EXTI_SWIER1_SWI7_Pos (7U)
7156#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)
7157#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk
7158#define EXTI_SWIER1_SWI8_Pos (8U)
7159#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)
7160#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk
7161#define EXTI_SWIER1_SWI9_Pos (9U)
7162#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)
7163#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk
7164#define EXTI_SWIER1_SWI10_Pos (10U)
7165#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)
7166#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk
7167#define EXTI_SWIER1_SWI11_Pos (11U)
7168#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)
7169#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk
7170#define EXTI_SWIER1_SWI12_Pos (12U)
7171#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)
7172#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk
7173#define EXTI_SWIER1_SWI13_Pos (13U)
7174#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)
7175#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk
7176#define EXTI_SWIER1_SWI14_Pos (14U)
7177#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)
7178#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk
7179#define EXTI_SWIER1_SWI15_Pos (15U)
7180#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)
7181#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk
7182#define EXTI_SWIER1_SWI16_Pos (16U)
7183#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos)
7184#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk
7185#define EXTI_SWIER1_SWI18_Pos (18U)
7186#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos)
7187#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk
7188#define EXTI_SWIER1_SWI19_Pos (19U)
7189#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos)
7190#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk
7191#define EXTI_SWIER1_SWI20_Pos (20U)
7192#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos)
7193#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk
7194#define EXTI_SWIER1_SWI21_Pos (21U)
7195#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos)
7196#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk
7197#define EXTI_SWIER1_SWI22_Pos (22U)
7198#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos)
7199#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk
7201/******************* Bit definition for EXTI_PR1 register *******************/
7202#define EXTI_PR1_PIF0_Pos (0U)
7203#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos)
7204#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk
7205#define EXTI_PR1_PIF1_Pos (1U)
7206#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos)
7207#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk
7208#define EXTI_PR1_PIF2_Pos (2U)
7209#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos)
7210#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk
7211#define EXTI_PR1_PIF3_Pos (3U)
7212#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos)
7213#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk
7214#define EXTI_PR1_PIF4_Pos (4U)
7215#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos)
7216#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk
7217#define EXTI_PR1_PIF5_Pos (5U)
7218#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos)
7219#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk
7220#define EXTI_PR1_PIF6_Pos (6U)
7221#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos)
7222#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk
7223#define EXTI_PR1_PIF7_Pos (7U)
7224#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos)
7225#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk
7226#define EXTI_PR1_PIF8_Pos (8U)
7227#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos)
7228#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk
7229#define EXTI_PR1_PIF9_Pos (9U)
7230#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos)
7231#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk
7232#define EXTI_PR1_PIF10_Pos (10U)
7233#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos)
7234#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk
7235#define EXTI_PR1_PIF11_Pos (11U)
7236#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos)
7237#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk
7238#define EXTI_PR1_PIF12_Pos (12U)
7239#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos)
7240#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk
7241#define EXTI_PR1_PIF13_Pos (13U)
7242#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos)
7243#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk
7244#define EXTI_PR1_PIF14_Pos (14U)
7245#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos)
7246#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk
7247#define EXTI_PR1_PIF15_Pos (15U)
7248#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos)
7249#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk
7250#define EXTI_PR1_PIF16_Pos (16U)
7251#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos)
7252#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk
7253#define EXTI_PR1_PIF18_Pos (18U)
7254#define EXTI_PR1_PIF18_Msk (0x1UL << EXTI_PR1_PIF18_Pos)
7255#define EXTI_PR1_PIF18 EXTI_PR1_PIF18_Msk
7256#define EXTI_PR1_PIF19_Pos (19U)
7257#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos)
7258#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk
7259#define EXTI_PR1_PIF20_Pos (20U)
7260#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos)
7261#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk
7262#define EXTI_PR1_PIF21_Pos (21U)
7263#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos)
7264#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk
7265#define EXTI_PR1_PIF22_Pos (22U)
7266#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos)
7267#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk
7269/******************* Bit definition for EXTI_IMR2 register ******************/
7270#define EXTI_IMR2_IM32_Pos (0U)
7271#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
7272#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
7273#define EXTI_IMR2_IM33_Pos (1U)
7274#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
7275#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
7276#define EXTI_IMR2_IM34_Pos (2U)
7277#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
7278#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
7279#define EXTI_IMR2_IM36_Pos (4U)
7280#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
7281#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
7282#define EXTI_IMR2_IM37_Pos (5U)
7283#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
7284#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
7285#define EXTI_IMR2_IM38_Pos (6U)
7286#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
7287#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
7288#define EXTI_IMR2_IM_Pos (0U)
7289#define EXTI_IMR2_IM_Msk (0x7EUL << EXTI_IMR2_IM_Pos)
7290#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
7292/******************* Bit definition for EXTI_EMR2 register ******************/
7293#define EXTI_EMR2_EM32_Pos (0U)
7294#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
7295#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
7296#define EXTI_EMR2_EM33_Pos (1U)
7297#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
7298#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
7299#define EXTI_EMR2_EM34_Pos (2U)
7300#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
7301#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
7302#define EXTI_EMR2_EM36_Pos (4U)
7303#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
7304#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
7305#define EXTI_EMR2_EM37_Pos (5U)
7306#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
7307#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
7308#define EXTI_EMR2_EM38_Pos (6U)
7309#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
7310#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
7311#define EXTI_EMR2_EM_Pos (0U)
7312#define EXTI_EMR2_EM_Msk (0x7EUL << EXTI_EMR2_EM_Pos)
7313#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
7315/****************** Bit definition for EXTI_RTSR2 register ******************/
7316#define EXTI_RTSR2_RT36_Pos (4U)
7317#define EXTI_RTSR2_RT36_Msk (0x1UL << EXTI_RTSR2_RT36_Pos)
7318#define EXTI_RTSR2_RT36 EXTI_RTSR2_RT36_Msk
7319#define EXTI_RTSR2_RT37_Pos (5U)
7320#define EXTI_RTSR2_RT37_Msk (0x1UL << EXTI_RTSR2_RT37_Pos)
7321#define EXTI_RTSR2_RT37 EXTI_RTSR2_RT37_Msk
7322#define EXTI_RTSR2_RT38_Pos (6U)
7323#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos)
7324#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk
7326/****************** Bit definition for EXTI_FTSR2 register ******************/
7327#define EXTI_FTSR2_FT36_Pos (4U)
7328#define EXTI_FTSR2_FT36_Msk (0x1UL << EXTI_FTSR2_FT36_Pos)
7329#define EXTI_FTSR2_FT36 EXTI_FTSR2_FT36_Msk
7330#define EXTI_FTSR2_FT37_Pos (5U)
7331#define EXTI_FTSR2_FT37_Msk (0x1UL << EXTI_FTSR2_FT37_Pos)
7332#define EXTI_FTSR2_FT37 EXTI_FTSR2_FT37_Msk
7333#define EXTI_FTSR2_FT38_Pos (6U)
7334#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos)
7335#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk
7337/****************** Bit definition for EXTI_SWIER2 register *****************/
7338#define EXTI_SWIER2_SWI36_Pos (4U)
7339#define EXTI_SWIER2_SWI36_Msk (0x1UL << EXTI_SWIER2_SWI36_Pos)
7340#define EXTI_SWIER2_SWI36 EXTI_SWIER2_SWI36_Msk
7341#define EXTI_SWIER2_SWI37_Pos (5U)
7342#define EXTI_SWIER2_SWI37_Msk (0x1UL << EXTI_SWIER2_SWI37_Pos)
7343#define EXTI_SWIER2_SWI37 EXTI_SWIER2_SWI37_Msk
7344#define EXTI_SWIER2_SWI38_Pos (6U)
7345#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos)
7346#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk
7348/******************* Bit definition for EXTI_PR2 register *******************/
7349#define EXTI_PR2_PIF36_Pos (4U)
7350#define EXTI_PR2_PIF36_Msk (0x1UL << EXTI_PR2_PIF36_Pos)
7351#define EXTI_PR2_PIF36 EXTI_PR2_PIF36_Msk
7352#define EXTI_PR2_PIF37_Pos (5U)
7353#define EXTI_PR2_PIF37_Msk (0x1UL << EXTI_PR2_PIF37_Pos)
7354#define EXTI_PR2_PIF37 EXTI_PR2_PIF37_Msk
7355#define EXTI_PR2_PIF38_Pos (6U)
7356#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos)
7357#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk
7360/******************************************************************************/
7361/* */
7362/* FLASH */
7363/* */
7364/******************************************************************************/
7365/******************* Bits definition for FLASH_ACR register *****************/
7366#define FLASH_ACR_LATENCY_Pos (0U)
7367#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
7368#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
7369#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
7370#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
7371#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
7372#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
7373#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
7374#define FLASH_ACR_PRFTEN_Pos (8U)
7375#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
7376#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
7377#define FLASH_ACR_ICEN_Pos (9U)
7378#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
7379#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
7380#define FLASH_ACR_DCEN_Pos (10U)
7381#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
7382#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
7383#define FLASH_ACR_ICRST_Pos (11U)
7384#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
7385#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
7386#define FLASH_ACR_DCRST_Pos (12U)
7387#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
7388#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
7389#define FLASH_ACR_RUN_PD_Pos (13U)
7390#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)
7391#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk
7392#define FLASH_ACR_SLEEP_PD_Pos (14U)
7393#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)
7394#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk
7396/******************* Bits definition for FLASH_SR register ******************/
7397#define FLASH_SR_EOP_Pos (0U)
7398#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
7399#define FLASH_SR_EOP FLASH_SR_EOP_Msk
7400#define FLASH_SR_OPERR_Pos (1U)
7401#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
7402#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
7403#define FLASH_SR_PROGERR_Pos (3U)
7404#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)
7405#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
7406#define FLASH_SR_WRPERR_Pos (4U)
7407#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
7408#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
7409#define FLASH_SR_PGAERR_Pos (5U)
7410#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
7411#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
7412#define FLASH_SR_SIZERR_Pos (6U)
7413#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)
7414#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
7415#define FLASH_SR_PGSERR_Pos (7U)
7416#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
7417#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
7418#define FLASH_SR_MISERR_Pos (8U)
7419#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)
7420#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
7421#define FLASH_SR_FASTERR_Pos (9U)
7422#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)
7423#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
7424#define FLASH_SR_RDERR_Pos (14U)
7425#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
7426#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
7427#define FLASH_SR_OPTVERR_Pos (15U)
7428#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)
7429#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
7430#define FLASH_SR_BSY_Pos (16U)
7431#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
7432#define FLASH_SR_BSY FLASH_SR_BSY_Msk
7433
7434/******************* Bits definition for FLASH_CR register ******************/
7435#define FLASH_CR_PG_Pos (0U)
7436#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
7437#define FLASH_CR_PG FLASH_CR_PG_Msk
7438#define FLASH_CR_PER_Pos (1U)
7439#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
7440#define FLASH_CR_PER FLASH_CR_PER_Msk
7441#define FLASH_CR_MER1_Pos (2U)
7442#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)
7443#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
7444#define FLASH_CR_PNB_Pos (3U)
7445#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos)
7446#define FLASH_CR_PNB FLASH_CR_PNB_Msk
7447#define FLASH_CR_BKER_Pos (11U)
7448#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos)
7449#define FLASH_CR_BKER FLASH_CR_BKER_Msk
7450#define FLASH_CR_MER2_Pos (15U)
7451#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
7452#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
7453#define FLASH_CR_STRT_Pos (16U)
7454#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
7455#define FLASH_CR_STRT FLASH_CR_STRT_Msk
7456#define FLASH_CR_OPTSTRT_Pos (17U)
7457#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)
7458#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
7459#define FLASH_CR_FSTPG_Pos (18U)
7460#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)
7461#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
7462#define FLASH_CR_EOPIE_Pos (24U)
7463#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
7464#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
7465#define FLASH_CR_ERRIE_Pos (25U)
7466#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
7467#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
7468#define FLASH_CR_RDERRIE_Pos (26U)
7469#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)
7470#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
7471#define FLASH_CR_OBL_LAUNCH_Pos (27U)
7472#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)
7473#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
7474#define FLASH_CR_OPTLOCK_Pos (30U)
7475#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)
7476#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
7477#define FLASH_CR_LOCK_Pos (31U)
7478#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
7479#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
7480
7481/******************* Bits definition for FLASH_ECCR register ***************/
7482#define FLASH_ECCR_ADDR_ECC_Pos (0U)
7483#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)
7484#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
7485#define FLASH_ECCR_BK_ECC_Pos (19U)
7486#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos)
7487#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
7488#define FLASH_ECCR_SYSF_ECC_Pos (20U)
7489#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)
7490#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
7491#define FLASH_ECCR_ECCIE_Pos (24U)
7492#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos)
7493#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
7494#define FLASH_ECCR_ECCC_Pos (30U)
7495#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)
7496#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
7497#define FLASH_ECCR_ECCD_Pos (31U)
7498#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)
7499#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
7500
7501/******************* Bits definition for FLASH_OPTR register ***************/
7502#define FLASH_OPTR_RDP_Pos (0U)
7503#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)
7504#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
7505#define FLASH_OPTR_BOR_LEV_Pos (8U)
7506#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos)
7507#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
7508#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos)
7509#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos)
7510#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos)
7511#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos)
7512#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos)
7513#define FLASH_OPTR_nRST_STOP_Pos (12U)
7514#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)
7515#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
7516#define FLASH_OPTR_nRST_STDBY_Pos (13U)
7517#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)
7518#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
7519#define FLASH_OPTR_nRST_SHDW_Pos (14U)
7520#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)
7521#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
7522#define FLASH_OPTR_IWDG_SW_Pos (16U)
7523#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)
7524#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
7525#define FLASH_OPTR_IWDG_STOP_Pos (17U)
7526#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)
7527#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
7528#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
7529#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)
7530#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
7531#define FLASH_OPTR_WWDG_SW_Pos (19U)
7532#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)
7533#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
7534#define FLASH_OPTR_BFB2_Pos (20U)
7535#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos)
7536#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
7537#define FLASH_OPTR_DUALBANK_Pos (21U)
7538#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos)
7539#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk
7540#define FLASH_OPTR_nBOOT1_Pos (23U)
7541#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)
7542#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
7543#define FLASH_OPTR_SRAM2_PE_Pos (24U)
7544#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos)
7545#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk
7546#define FLASH_OPTR_SRAM2_RST_Pos (25U)
7547#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos)
7548#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk
7549
7550/****************** Bits definition for FLASH_PCROP1SR register **********/
7551#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
7552#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0xFFFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)
7553#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
7554
7555/****************** Bits definition for FLASH_PCROP1ER register ***********/
7556#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
7557#define FLASH_PCROP1ER_PCROP1_END_Msk (0xFFFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)
7558#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
7559#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
7560#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)
7561#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
7562
7563/****************** Bits definition for FLASH_WRP1AR register ***************/
7564#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
7565#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_STRT_Pos)
7566#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
7567#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
7568#define FLASH_WRP1AR_WRP1A_END_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_END_Pos)
7569#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
7570
7571/****************** Bits definition for FLASH_WRPB1R register ***************/
7572#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
7573#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_STRT_Pos)
7574#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
7575#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
7576#define FLASH_WRP1BR_WRP1B_END_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_END_Pos)
7577#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
7578
7579/****************** Bits definition for FLASH_PCROP2SR register **********/
7580#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
7581#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0xFFFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)
7582#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
7583
7584/****************** Bits definition for FLASH_PCROP2ER register ***********/
7585#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
7586#define FLASH_PCROP2ER_PCROP2_END_Msk (0xFFFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)
7587#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
7588
7589/****************** Bits definition for FLASH_WRP2AR register ***************/
7590#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
7591#define FLASH_WRP2AR_WRP2A_STRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_STRT_Pos)
7592#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
7593#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
7594#define FLASH_WRP2AR_WRP2A_END_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_END_Pos)
7595#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
7596
7597/****************** Bits definition for FLASH_WRP2BR register ***************/
7598#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
7599#define FLASH_WRP2BR_WRP2B_STRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_STRT_Pos)
7600#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
7601#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
7602#define FLASH_WRP2BR_WRP2B_END_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_END_Pos)
7603#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
7604
7605
7606/******************************************************************************/
7607/* */
7608/* Flexible Memory Controller */
7609/* */
7610/******************************************************************************/
7611/****************** Bit definition for FMC_BCR1 register *******************/
7612#define FMC_BCR1_CCLKEN_Pos (20U)
7613#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
7614#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
7616/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
7617#define FMC_BCRx_MBKEN_Pos (0U)
7618#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
7619#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
7620#define FMC_BCRx_MUXEN_Pos (1U)
7621#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
7622#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
7624#define FMC_BCRx_MTYP_Pos (2U)
7625#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
7626#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
7627#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
7628#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
7630#define FMC_BCRx_MWID_Pos (4U)
7631#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
7632#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
7633#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
7634#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
7636#define FMC_BCRx_FACCEN_Pos (6U)
7637#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
7638#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
7639#define FMC_BCRx_BURSTEN_Pos (8U)
7640#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
7641#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
7642#define FMC_BCRx_WAITPOL_Pos (9U)
7643#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
7644#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
7645#define FMC_BCRx_WAITCFG_Pos (11U)
7646#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
7647#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
7648#define FMC_BCRx_WREN_Pos (12U)
7649#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
7650#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
7651#define FMC_BCRx_WAITEN_Pos (13U)
7652#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
7653#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
7654#define FMC_BCRx_EXTMOD_Pos (14U)
7655#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
7656#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
7657#define FMC_BCRx_ASYNCWAIT_Pos (15U)
7658#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
7659#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
7661#define FMC_BCRx_CPSIZE_Pos (16U)
7662#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
7663#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
7664#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
7665#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
7666#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
7668#define FMC_BCRx_CBURSTRW_Pos (19U)
7669#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
7670#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
7672/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
7673#define FMC_BTRx_ADDSET_Pos (0U)
7674#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
7675#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
7676#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
7677#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
7678#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
7679#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
7681#define FMC_BTRx_ADDHLD_Pos (4U)
7682#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
7683#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
7684#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
7685#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
7686#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
7687#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
7689#define FMC_BTRx_DATAST_Pos (8U)
7690#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
7691#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
7692#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
7693#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
7694#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
7695#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
7696#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
7697#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
7698#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
7699#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
7701#define FMC_BTRx_BUSTURN_Pos (16U)
7702#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
7703#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
7704#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
7705#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
7706#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
7707#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
7709#define FMC_BTRx_CLKDIV_Pos (20U)
7710#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
7711#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
7712#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
7713#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
7714#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
7715#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
7717#define FMC_BTRx_DATLAT_Pos (24U)
7718#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
7719#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
7720#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
7721#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
7722#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
7723#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
7725#define FMC_BTRx_ACCMOD_Pos (28U)
7726#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
7727#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
7728#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
7729#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
7731/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
7732#define FMC_BWTRx_ADDSET_Pos (0U)
7733#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
7734#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
7735#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
7736#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
7737#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
7738#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
7740#define FMC_BWTRx_ADDHLD_Pos (4U)
7741#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
7742#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
7743#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
7744#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
7745#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
7746#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
7748#define FMC_BWTRx_DATAST_Pos (8U)
7749#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
7750#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
7751#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
7752#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
7753#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
7754#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
7755#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
7756#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
7757#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
7758#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
7760#define FMC_BWTRx_BUSTURN_Pos (16U)
7761#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
7762#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
7763#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
7764#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
7765#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
7766#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
7768#define FMC_BWTRx_ACCMOD_Pos (28U)
7769#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
7770#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
7771#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
7772#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
7774/****************** Bit definition for FMC_PCR register ********************/
7775#define FMC_PCR_PWAITEN_Pos (1U)
7776#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
7777#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
7778#define FMC_PCR_PBKEN_Pos (2U)
7779#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
7780#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
7781#define FMC_PCR_PTYP_Pos (3U)
7782#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
7783#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
7785#define FMC_PCR_PWID_Pos (4U)
7786#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
7787#define FMC_PCR_PWID FMC_PCR_PWID_Msk
7788#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
7789#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
7791#define FMC_PCR_ECCEN_Pos (6U)
7792#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
7793#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
7795#define FMC_PCR_TCLR_Pos (9U)
7796#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
7797#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
7798#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
7799#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
7800#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
7801#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
7803#define FMC_PCR_TAR_Pos (13U)
7804#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
7805#define FMC_PCR_TAR FMC_PCR_TAR_Msk
7806#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
7807#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
7808#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
7809#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
7811#define FMC_PCR_ECCPS_Pos (17U)
7812#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
7813#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
7814#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
7815#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
7816#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
7818/******************* Bit definition for FMC_SR register ********************/
7819#define FMC_SR_IRS_Pos (0U)
7820#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
7821#define FMC_SR_IRS FMC_SR_IRS_Msk
7822#define FMC_SR_ILS_Pos (1U)
7823#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
7824#define FMC_SR_ILS FMC_SR_ILS_Msk
7825#define FMC_SR_IFS_Pos (2U)
7826#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
7827#define FMC_SR_IFS FMC_SR_IFS_Msk
7828#define FMC_SR_IREN_Pos (3U)
7829#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
7830#define FMC_SR_IREN FMC_SR_IREN_Msk
7831#define FMC_SR_ILEN_Pos (4U)
7832#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
7833#define FMC_SR_ILEN FMC_SR_ILEN_Msk
7834#define FMC_SR_IFEN_Pos (5U)
7835#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
7836#define FMC_SR_IFEN FMC_SR_IFEN_Msk
7837#define FMC_SR_FEMPT_Pos (6U)
7838#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
7839#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
7841/****************** Bit definition for FMC_PMEM register ******************/
7842#define FMC_PMEM_MEMSET_Pos (0U)
7843#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
7844#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
7845#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
7846#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
7847#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
7848#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
7849#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
7850#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
7851#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
7852#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
7854#define FMC_PMEM_MEMWAIT_Pos (8U)
7855#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
7856#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
7857#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
7858#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
7859#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
7860#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
7861#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
7862#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
7863#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
7864#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
7866#define FMC_PMEM_MEMHOLD_Pos (16U)
7867#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
7868#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
7869#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
7870#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
7871#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
7872#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
7873#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
7874#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
7875#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
7876#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
7878#define FMC_PMEM_MEMHIZ_Pos (24U)
7879#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
7880#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
7881#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
7882#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
7883#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
7884#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
7885#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
7886#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
7887#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
7888#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
7890/****************** Bit definition for FMC_PATT register *******************/
7891#define FMC_PATT_ATTSET_Pos (0U)
7892#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
7893#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
7894#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
7895#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
7896#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
7897#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
7898#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
7899#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
7900#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
7901#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
7903#define FMC_PATT_ATTWAIT_Pos (8U)
7904#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
7905#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
7906#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
7907#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
7908#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
7909#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
7910#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
7911#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
7912#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
7913#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
7915#define FMC_PATT_ATTHOLD_Pos (16U)
7916#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
7917#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
7918#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
7919#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
7920#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
7921#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
7922#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
7923#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
7924#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
7925#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
7927#define FMC_PATT_ATTHIZ_Pos (24U)
7928#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
7929#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
7930#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
7931#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
7932#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
7933#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
7934#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
7935#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
7936#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
7937#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
7939/****************** Bit definition for FMC_ECCR register *******************/
7940#define FMC_ECCR_ECC_Pos (0U)
7941#define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos)
7942#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk
7944/******************************************************************************/
7945/* */
7946/* General Purpose IOs (GPIO) */
7947/* */
7948/******************************************************************************/
7949/****************** Bits definition for GPIO_MODER register *****************/
7950#define GPIO_MODER_MODE0_Pos (0U)
7951#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
7952#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
7953#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
7954#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
7955#define GPIO_MODER_MODE1_Pos (2U)
7956#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
7957#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
7958#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
7959#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
7960#define GPIO_MODER_MODE2_Pos (4U)
7961#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
7962#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
7963#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
7964#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
7965#define GPIO_MODER_MODE3_Pos (6U)
7966#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
7967#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
7968#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
7969#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
7970#define GPIO_MODER_MODE4_Pos (8U)
7971#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
7972#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
7973#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
7974#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
7975#define GPIO_MODER_MODE5_Pos (10U)
7976#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
7977#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
7978#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
7979#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
7980#define GPIO_MODER_MODE6_Pos (12U)
7981#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
7982#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
7983#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
7984#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
7985#define GPIO_MODER_MODE7_Pos (14U)
7986#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
7987#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
7988#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
7989#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
7990#define GPIO_MODER_MODE8_Pos (16U)
7991#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
7992#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
7993#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
7994#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
7995#define GPIO_MODER_MODE9_Pos (18U)
7996#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
7997#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
7998#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
7999#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
8000#define GPIO_MODER_MODE10_Pos (20U)
8001#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
8002#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
8003#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
8004#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
8005#define GPIO_MODER_MODE11_Pos (22U)
8006#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
8007#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
8008#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
8009#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
8010#define GPIO_MODER_MODE12_Pos (24U)
8011#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
8012#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
8013#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
8014#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
8015#define GPIO_MODER_MODE13_Pos (26U)
8016#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
8017#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
8018#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
8019#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
8020#define GPIO_MODER_MODE14_Pos (28U)
8021#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
8022#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
8023#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
8024#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
8025#define GPIO_MODER_MODE15_Pos (30U)
8026#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
8027#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
8028#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
8029#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
8031/* Legacy defines */
8032#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
8033#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
8034#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
8035#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
8036#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
8037#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
8038#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
8039#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
8040#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
8041#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
8042#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
8043#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
8044#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
8045#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
8046#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
8047#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
8048#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
8049#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
8050#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
8051#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
8052#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
8053#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
8054#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
8055#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
8056#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
8057#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
8058#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
8059#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
8060#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
8061#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
8062#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
8063#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
8064#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
8065#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
8066#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
8067#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
8068#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
8069#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
8070#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
8071#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
8072#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
8073#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
8074#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
8075#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
8076#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
8077#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
8078#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
8079#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
8080
8081/****************** Bits definition for GPIO_OTYPER register ****************/
8082#define GPIO_OTYPER_OT0_Pos (0U)
8083#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
8084#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
8085#define GPIO_OTYPER_OT1_Pos (1U)
8086#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
8087#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
8088#define GPIO_OTYPER_OT2_Pos (2U)
8089#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
8090#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
8091#define GPIO_OTYPER_OT3_Pos (3U)
8092#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
8093#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
8094#define GPIO_OTYPER_OT4_Pos (4U)
8095#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
8096#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
8097#define GPIO_OTYPER_OT5_Pos (5U)
8098#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
8099#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
8100#define GPIO_OTYPER_OT6_Pos (6U)
8101#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
8102#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
8103#define GPIO_OTYPER_OT7_Pos (7U)
8104#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
8105#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
8106#define GPIO_OTYPER_OT8_Pos (8U)
8107#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
8108#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
8109#define GPIO_OTYPER_OT9_Pos (9U)
8110#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
8111#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
8112#define GPIO_OTYPER_OT10_Pos (10U)
8113#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
8114#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
8115#define GPIO_OTYPER_OT11_Pos (11U)
8116#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
8117#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
8118#define GPIO_OTYPER_OT12_Pos (12U)
8119#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
8120#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
8121#define GPIO_OTYPER_OT13_Pos (13U)
8122#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
8123#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
8124#define GPIO_OTYPER_OT14_Pos (14U)
8125#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
8126#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
8127#define GPIO_OTYPER_OT15_Pos (15U)
8128#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
8129#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
8130
8131/* Legacy defines */
8132#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
8133#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
8134#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
8135#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
8136#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
8137#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
8138#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
8139#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
8140#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
8141#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
8142#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
8143#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
8144#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
8145#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
8146#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
8147#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
8148
8149/****************** Bits definition for GPIO_OSPEEDR register ***************/
8150#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
8151#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
8152#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
8153#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
8154#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
8155#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
8156#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
8157#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
8158#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
8159#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
8160#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
8161#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
8162#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
8163#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
8164#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
8165#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
8166#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
8167#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
8168#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
8169#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
8170#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
8171#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
8172#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
8173#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
8174#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
8175#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
8176#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
8177#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
8178#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
8179#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
8180#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
8181#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
8182#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
8183#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
8184#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
8185#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
8186#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
8187#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
8188#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
8189#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
8190#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
8191#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
8192#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
8193#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
8194#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
8195#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
8196#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
8197#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
8198#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
8199#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
8200#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
8201#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
8202#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
8203#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
8204#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
8205#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
8206#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
8207#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
8208#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
8209#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
8210#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
8211#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
8212#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
8213#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
8214#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
8215#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
8216#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
8217#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
8218#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
8219#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
8220#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
8221#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
8222#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
8223#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
8224#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
8225#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
8226#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
8227#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
8228#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
8229#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
8231/* Legacy defines */
8232#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
8233#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
8234#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
8235#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
8236#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
8237#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
8238#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
8239#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
8240#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
8241#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
8242#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
8243#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
8244#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
8245#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
8246#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
8247#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
8248#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
8249#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
8250#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
8251#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
8252#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
8253#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
8254#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
8255#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
8256#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
8257#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
8258#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
8259#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
8260#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
8261#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
8262#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
8263#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
8264#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
8265#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
8266#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
8267#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
8268#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
8269#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
8270#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
8271#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
8272#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
8273#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
8274#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
8275#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
8276#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
8277#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
8278#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
8279#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
8280
8281/****************** Bits definition for GPIO_PUPDR register *****************/
8282#define GPIO_PUPDR_PUPD0_Pos (0U)
8283#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
8284#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
8285#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
8286#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
8287#define GPIO_PUPDR_PUPD1_Pos (2U)
8288#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
8289#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
8290#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
8291#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
8292#define GPIO_PUPDR_PUPD2_Pos (4U)
8293#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
8294#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
8295#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
8296#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
8297#define GPIO_PUPDR_PUPD3_Pos (6U)
8298#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
8299#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
8300#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
8301#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
8302#define GPIO_PUPDR_PUPD4_Pos (8U)
8303#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
8304#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
8305#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
8306#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
8307#define GPIO_PUPDR_PUPD5_Pos (10U)
8308#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
8309#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
8310#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
8311#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
8312#define GPIO_PUPDR_PUPD6_Pos (12U)
8313#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
8314#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
8315#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
8316#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
8317#define GPIO_PUPDR_PUPD7_Pos (14U)
8318#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
8319#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
8320#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
8321#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
8322#define GPIO_PUPDR_PUPD8_Pos (16U)
8323#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
8324#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
8325#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
8326#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
8327#define GPIO_PUPDR_PUPD9_Pos (18U)
8328#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
8329#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
8330#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
8331#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
8332#define GPIO_PUPDR_PUPD10_Pos (20U)
8333#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
8334#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
8335#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
8336#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
8337#define GPIO_PUPDR_PUPD11_Pos (22U)
8338#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
8339#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
8340#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
8341#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
8342#define GPIO_PUPDR_PUPD12_Pos (24U)
8343#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
8344#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
8345#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
8346#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
8347#define GPIO_PUPDR_PUPD13_Pos (26U)
8348#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
8349#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
8350#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
8351#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
8352#define GPIO_PUPDR_PUPD14_Pos (28U)
8353#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
8354#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
8355#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
8356#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
8357#define GPIO_PUPDR_PUPD15_Pos (30U)
8358#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
8359#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
8360#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
8361#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
8363/* Legacy defines */
8364#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
8365#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
8366#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
8367#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
8368#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
8369#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
8370#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
8371#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
8372#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
8373#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
8374#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
8375#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
8376#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
8377#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
8378#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
8379#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
8380#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
8381#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
8382#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
8383#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
8384#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
8385#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
8386#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
8387#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
8388#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
8389#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
8390#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
8391#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
8392#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
8393#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
8394#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
8395#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
8396#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
8397#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
8398#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
8399#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
8400#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
8401#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
8402#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
8403#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
8404#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
8405#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
8406#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
8407#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
8408#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
8409#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
8410#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
8411#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
8412
8413/****************** Bits definition for GPIO_IDR register *******************/
8414#define GPIO_IDR_ID0_Pos (0U)
8415#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
8416#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
8417#define GPIO_IDR_ID1_Pos (1U)
8418#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
8419#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
8420#define GPIO_IDR_ID2_Pos (2U)
8421#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
8422#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
8423#define GPIO_IDR_ID3_Pos (3U)
8424#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
8425#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
8426#define GPIO_IDR_ID4_Pos (4U)
8427#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
8428#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
8429#define GPIO_IDR_ID5_Pos (5U)
8430#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
8431#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
8432#define GPIO_IDR_ID6_Pos (6U)
8433#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
8434#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
8435#define GPIO_IDR_ID7_Pos (7U)
8436#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
8437#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
8438#define GPIO_IDR_ID8_Pos (8U)
8439#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
8440#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
8441#define GPIO_IDR_ID9_Pos (9U)
8442#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
8443#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
8444#define GPIO_IDR_ID10_Pos (10U)
8445#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
8446#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
8447#define GPIO_IDR_ID11_Pos (11U)
8448#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
8449#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
8450#define GPIO_IDR_ID12_Pos (12U)
8451#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
8452#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
8453#define GPIO_IDR_ID13_Pos (13U)
8454#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
8455#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
8456#define GPIO_IDR_ID14_Pos (14U)
8457#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
8458#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
8459#define GPIO_IDR_ID15_Pos (15U)
8460#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
8461#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
8462
8463/* Legacy defines */
8464#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
8465#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
8466#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
8467#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
8468#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
8469#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
8470#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
8471#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
8472#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
8473#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
8474#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
8475#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
8476#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
8477#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
8478#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
8479#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
8480
8481/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
8482#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
8483#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
8484#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
8485#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
8486#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
8487#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
8488#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
8489#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
8490#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
8491#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
8492#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
8493#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
8494#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
8495#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
8496#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
8497#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
8498
8499/****************** Bits definition for GPIO_ODR register *******************/
8500#define GPIO_ODR_OD0_Pos (0U)
8501#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
8502#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
8503#define GPIO_ODR_OD1_Pos (1U)
8504#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
8505#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
8506#define GPIO_ODR_OD2_Pos (2U)
8507#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
8508#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
8509#define GPIO_ODR_OD3_Pos (3U)
8510#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
8511#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
8512#define GPIO_ODR_OD4_Pos (4U)
8513#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
8514#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
8515#define GPIO_ODR_OD5_Pos (5U)
8516#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
8517#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
8518#define GPIO_ODR_OD6_Pos (6U)
8519#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
8520#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
8521#define GPIO_ODR_OD7_Pos (7U)
8522#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
8523#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8524#define GPIO_ODR_OD8_Pos (8U)
8525#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8526#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8527#define GPIO_ODR_OD9_Pos (9U)
8528#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8529#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8530#define GPIO_ODR_OD10_Pos (10U)
8531#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8532#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8533#define GPIO_ODR_OD11_Pos (11U)
8534#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8535#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8536#define GPIO_ODR_OD12_Pos (12U)
8537#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8538#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8539#define GPIO_ODR_OD13_Pos (13U)
8540#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8541#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8542#define GPIO_ODR_OD14_Pos (14U)
8543#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8544#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8545#define GPIO_ODR_OD15_Pos (15U)
8546#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8547#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8548
8549/* Legacy defines */
8550#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8551#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8552#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8553#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8554#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8555#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8556#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8557#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8558#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8559#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8560#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8561#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8562#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8563#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8564#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8565#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8566
8567/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
8568#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
8569#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
8570#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
8571#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
8572#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
8573#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
8574#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
8575#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
8576#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
8577#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
8578#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
8579#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
8580#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
8581#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
8582#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
8583#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
8584
8585/****************** Bits definition for GPIO_BSRR register ******************/
8586#define GPIO_BSRR_BS0_Pos (0U)
8587#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8588#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8589#define GPIO_BSRR_BS1_Pos (1U)
8590#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8591#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8592#define GPIO_BSRR_BS2_Pos (2U)
8593#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8594#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8595#define GPIO_BSRR_BS3_Pos (3U)
8596#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8597#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8598#define GPIO_BSRR_BS4_Pos (4U)
8599#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8600#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8601#define GPIO_BSRR_BS5_Pos (5U)
8602#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8603#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8604#define GPIO_BSRR_BS6_Pos (6U)
8605#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8606#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8607#define GPIO_BSRR_BS7_Pos (7U)
8608#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8609#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8610#define GPIO_BSRR_BS8_Pos (8U)
8611#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8612#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8613#define GPIO_BSRR_BS9_Pos (9U)
8614#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8615#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8616#define GPIO_BSRR_BS10_Pos (10U)
8617#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8618#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8619#define GPIO_BSRR_BS11_Pos (11U)
8620#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8621#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8622#define GPIO_BSRR_BS12_Pos (12U)
8623#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8624#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8625#define GPIO_BSRR_BS13_Pos (13U)
8626#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8627#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8628#define GPIO_BSRR_BS14_Pos (14U)
8629#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8630#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8631#define GPIO_BSRR_BS15_Pos (15U)
8632#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8633#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8634#define GPIO_BSRR_BR0_Pos (16U)
8635#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8636#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8637#define GPIO_BSRR_BR1_Pos (17U)
8638#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8639#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8640#define GPIO_BSRR_BR2_Pos (18U)
8641#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8642#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8643#define GPIO_BSRR_BR3_Pos (19U)
8644#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8645#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8646#define GPIO_BSRR_BR4_Pos (20U)
8647#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8648#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8649#define GPIO_BSRR_BR5_Pos (21U)
8650#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8651#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8652#define GPIO_BSRR_BR6_Pos (22U)
8653#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8654#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8655#define GPIO_BSRR_BR7_Pos (23U)
8656#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8657#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8658#define GPIO_BSRR_BR8_Pos (24U)
8659#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8660#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8661#define GPIO_BSRR_BR9_Pos (25U)
8662#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8663#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8664#define GPIO_BSRR_BR10_Pos (26U)
8665#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8666#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8667#define GPIO_BSRR_BR11_Pos (27U)
8668#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8669#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8670#define GPIO_BSRR_BR12_Pos (28U)
8671#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8672#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8673#define GPIO_BSRR_BR13_Pos (29U)
8674#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8675#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8676#define GPIO_BSRR_BR14_Pos (30U)
8677#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8678#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8679#define GPIO_BSRR_BR15_Pos (31U)
8680#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8681#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8682
8683/* Legacy defines */
8684#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8685#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8686#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8687#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8688#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8689#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8690#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8691#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8692#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8693#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8694#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8695#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8696#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8697#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8698#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8699#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8700#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8701#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8702#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8703#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8704#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8705#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8706#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8707#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8708#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8709#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8710#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8711#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8712#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8713#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8714#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8715#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8716
8717/****************** Bit definition for GPIO_LCKR register *********************/
8718#define GPIO_LCKR_LCK0_Pos (0U)
8719#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8720#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8721#define GPIO_LCKR_LCK1_Pos (1U)
8722#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8723#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8724#define GPIO_LCKR_LCK2_Pos (2U)
8725#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8726#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8727#define GPIO_LCKR_LCK3_Pos (3U)
8728#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8729#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8730#define GPIO_LCKR_LCK4_Pos (4U)
8731#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8732#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8733#define GPIO_LCKR_LCK5_Pos (5U)
8734#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8735#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8736#define GPIO_LCKR_LCK6_Pos (6U)
8737#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8738#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8739#define GPIO_LCKR_LCK7_Pos (7U)
8740#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8741#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8742#define GPIO_LCKR_LCK8_Pos (8U)
8743#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8744#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8745#define GPIO_LCKR_LCK9_Pos (9U)
8746#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8747#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8748#define GPIO_LCKR_LCK10_Pos (10U)
8749#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8750#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8751#define GPIO_LCKR_LCK11_Pos (11U)
8752#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8753#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8754#define GPIO_LCKR_LCK12_Pos (12U)
8755#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8756#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8757#define GPIO_LCKR_LCK13_Pos (13U)
8758#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8759#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8760#define GPIO_LCKR_LCK14_Pos (14U)
8761#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8762#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8763#define GPIO_LCKR_LCK15_Pos (15U)
8764#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8765#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8766#define GPIO_LCKR_LCKK_Pos (16U)
8767#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8768#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8769
8770/****************** Bit definition for GPIO_AFRL register *********************/
8771#define GPIO_AFRL_AFSEL0_Pos (0U)
8772#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
8773#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
8774#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
8775#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
8776#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
8777#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
8778#define GPIO_AFRL_AFSEL1_Pos (4U)
8779#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
8780#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
8781#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
8782#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
8783#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
8784#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
8785#define GPIO_AFRL_AFSEL2_Pos (8U)
8786#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
8787#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
8788#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
8789#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
8790#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
8791#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
8792#define GPIO_AFRL_AFSEL3_Pos (12U)
8793#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
8794#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
8795#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
8796#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
8797#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
8798#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
8799#define GPIO_AFRL_AFSEL4_Pos (16U)
8800#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
8801#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
8802#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
8803#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
8804#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
8805#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
8806#define GPIO_AFRL_AFSEL5_Pos (20U)
8807#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
8808#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
8809#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
8810#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
8811#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
8812#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
8813#define GPIO_AFRL_AFSEL6_Pos (24U)
8814#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
8815#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
8816#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
8817#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
8818#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
8819#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
8820#define GPIO_AFRL_AFSEL7_Pos (28U)
8821#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
8822#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
8823#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
8824#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
8825#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
8826#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
8828/* Legacy defines */
8829#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
8830#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
8831#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
8832#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
8833#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
8834#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
8835#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
8836#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
8837
8838/****************** Bit definition for GPIO_AFRH register *********************/
8839#define GPIO_AFRH_AFSEL8_Pos (0U)
8840#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
8841#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
8842#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
8843#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
8844#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
8845#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
8846#define GPIO_AFRH_AFSEL9_Pos (4U)
8847#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
8848#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
8849#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
8850#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
8851#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
8852#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
8853#define GPIO_AFRH_AFSEL10_Pos (8U)
8854#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
8855#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
8856#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
8857#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
8858#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
8859#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
8860#define GPIO_AFRH_AFSEL11_Pos (12U)
8861#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
8862#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
8863#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
8864#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
8865#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
8866#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
8867#define GPIO_AFRH_AFSEL12_Pos (16U)
8868#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
8869#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
8870#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
8871#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
8872#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
8873#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
8874#define GPIO_AFRH_AFSEL13_Pos (20U)
8875#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
8876#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
8877#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
8878#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
8879#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
8880#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
8881#define GPIO_AFRH_AFSEL14_Pos (24U)
8882#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
8883#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
8884#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
8885#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
8886#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
8887#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
8888#define GPIO_AFRH_AFSEL15_Pos (28U)
8889#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
8890#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
8891#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
8892#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
8893#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
8894#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
8896/* Legacy defines */
8897#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
8898#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
8899#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
8900#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
8901#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
8902#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
8903#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
8904#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
8905
8906/****************** Bits definition for GPIO_BRR register ******************/
8907#define GPIO_BRR_BR0_Pos (0U)
8908#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)
8909#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
8910#define GPIO_BRR_BR1_Pos (1U)
8911#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)
8912#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
8913#define GPIO_BRR_BR2_Pos (2U)
8914#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)
8915#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
8916#define GPIO_BRR_BR3_Pos (3U)
8917#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)
8918#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
8919#define GPIO_BRR_BR4_Pos (4U)
8920#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)
8921#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
8922#define GPIO_BRR_BR5_Pos (5U)
8923#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)
8924#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
8925#define GPIO_BRR_BR6_Pos (6U)
8926#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)
8927#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
8928#define GPIO_BRR_BR7_Pos (7U)
8929#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)
8930#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
8931#define GPIO_BRR_BR8_Pos (8U)
8932#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)
8933#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
8934#define GPIO_BRR_BR9_Pos (9U)
8935#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)
8936#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
8937#define GPIO_BRR_BR10_Pos (10U)
8938#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)
8939#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
8940#define GPIO_BRR_BR11_Pos (11U)
8941#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)
8942#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
8943#define GPIO_BRR_BR12_Pos (12U)
8944#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)
8945#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
8946#define GPIO_BRR_BR13_Pos (13U)
8947#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)
8948#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
8949#define GPIO_BRR_BR14_Pos (14U)
8950#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)
8951#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
8952#define GPIO_BRR_BR15_Pos (15U)
8953#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)
8954#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
8955
8956/* Legacy defines */
8957#define GPIO_BRR_BR_0 GPIO_BRR_BR0
8958#define GPIO_BRR_BR_1 GPIO_BRR_BR1
8959#define GPIO_BRR_BR_2 GPIO_BRR_BR2
8960#define GPIO_BRR_BR_3 GPIO_BRR_BR3
8961#define GPIO_BRR_BR_4 GPIO_BRR_BR4
8962#define GPIO_BRR_BR_5 GPIO_BRR_BR5
8963#define GPIO_BRR_BR_6 GPIO_BRR_BR6
8964#define GPIO_BRR_BR_7 GPIO_BRR_BR7
8965#define GPIO_BRR_BR_8 GPIO_BRR_BR8
8966#define GPIO_BRR_BR_9 GPIO_BRR_BR9
8967#define GPIO_BRR_BR_10 GPIO_BRR_BR10
8968#define GPIO_BRR_BR_11 GPIO_BRR_BR11
8969#define GPIO_BRR_BR_12 GPIO_BRR_BR12
8970#define GPIO_BRR_BR_13 GPIO_BRR_BR13
8971#define GPIO_BRR_BR_14 GPIO_BRR_BR14
8972#define GPIO_BRR_BR_15 GPIO_BRR_BR15
8973
8974
8975/****************** Bits definition for GPIO_ASCR register *******************/
8976#define GPIO_ASCR_ASC0_Pos (0U)
8977#define GPIO_ASCR_ASC0_Msk (0x1UL << GPIO_ASCR_ASC0_Pos)
8978#define GPIO_ASCR_ASC0 GPIO_ASCR_ASC0_Msk
8979#define GPIO_ASCR_ASC1_Pos (1U)
8980#define GPIO_ASCR_ASC1_Msk (0x1UL << GPIO_ASCR_ASC1_Pos)
8981#define GPIO_ASCR_ASC1 GPIO_ASCR_ASC1_Msk
8982#define GPIO_ASCR_ASC2_Pos (2U)
8983#define GPIO_ASCR_ASC2_Msk (0x1UL << GPIO_ASCR_ASC2_Pos)
8984#define GPIO_ASCR_ASC2 GPIO_ASCR_ASC2_Msk
8985#define GPIO_ASCR_ASC3_Pos (3U)
8986#define GPIO_ASCR_ASC3_Msk (0x1UL << GPIO_ASCR_ASC3_Pos)
8987#define GPIO_ASCR_ASC3 GPIO_ASCR_ASC3_Msk
8988#define GPIO_ASCR_ASC4_Pos (4U)
8989#define GPIO_ASCR_ASC4_Msk (0x1UL << GPIO_ASCR_ASC4_Pos)
8990#define GPIO_ASCR_ASC4 GPIO_ASCR_ASC4_Msk
8991#define GPIO_ASCR_ASC5_Pos (5U)
8992#define GPIO_ASCR_ASC5_Msk (0x1UL << GPIO_ASCR_ASC5_Pos)
8993#define GPIO_ASCR_ASC5 GPIO_ASCR_ASC5_Msk
8994#define GPIO_ASCR_ASC6_Pos (6U)
8995#define GPIO_ASCR_ASC6_Msk (0x1UL << GPIO_ASCR_ASC6_Pos)
8996#define GPIO_ASCR_ASC6 GPIO_ASCR_ASC6_Msk
8997#define GPIO_ASCR_ASC7_Pos (7U)
8998#define GPIO_ASCR_ASC7_Msk (0x1UL << GPIO_ASCR_ASC7_Pos)
8999#define GPIO_ASCR_ASC7 GPIO_ASCR_ASC7_Msk
9000#define GPIO_ASCR_ASC8_Pos (8U)
9001#define GPIO_ASCR_ASC8_Msk (0x1UL << GPIO_ASCR_ASC8_Pos)
9002#define GPIO_ASCR_ASC8 GPIO_ASCR_ASC8_Msk
9003#define GPIO_ASCR_ASC9_Pos (9U)
9004#define GPIO_ASCR_ASC9_Msk (0x1UL << GPIO_ASCR_ASC9_Pos)
9005#define GPIO_ASCR_ASC9 GPIO_ASCR_ASC9_Msk
9006#define GPIO_ASCR_ASC10_Pos (10U)
9007#define GPIO_ASCR_ASC10_Msk (0x1UL << GPIO_ASCR_ASC10_Pos)
9008#define GPIO_ASCR_ASC10 GPIO_ASCR_ASC10_Msk
9009#define GPIO_ASCR_ASC11_Pos (11U)
9010#define GPIO_ASCR_ASC11_Msk (0x1UL << GPIO_ASCR_ASC11_Pos)
9011#define GPIO_ASCR_ASC11 GPIO_ASCR_ASC11_Msk
9012#define GPIO_ASCR_ASC12_Pos (12U)
9013#define GPIO_ASCR_ASC12_Msk (0x1UL << GPIO_ASCR_ASC12_Pos)
9014#define GPIO_ASCR_ASC12 GPIO_ASCR_ASC12_Msk
9015#define GPIO_ASCR_ASC13_Pos (13U)
9016#define GPIO_ASCR_ASC13_Msk (0x1UL << GPIO_ASCR_ASC13_Pos)
9017#define GPIO_ASCR_ASC13 GPIO_ASCR_ASC13_Msk
9018#define GPIO_ASCR_ASC14_Pos (14U)
9019#define GPIO_ASCR_ASC14_Msk (0x1UL << GPIO_ASCR_ASC14_Pos)
9020#define GPIO_ASCR_ASC14 GPIO_ASCR_ASC14_Msk
9021#define GPIO_ASCR_ASC15_Pos (15U)
9022#define GPIO_ASCR_ASC15_Msk (0x1UL << GPIO_ASCR_ASC15_Pos)
9023#define GPIO_ASCR_ASC15 GPIO_ASCR_ASC15_Msk
9024
9025/* Legacy defines */
9026#define GPIO_ASCR_EN_0 GPIO_ASCR_ASC0
9027#define GPIO_ASCR_EN_1 GPIO_ASCR_ASC1
9028#define GPIO_ASCR_EN_2 GPIO_ASCR_ASC2
9029#define GPIO_ASCR_EN_3 GPIO_ASCR_ASC3
9030#define GPIO_ASCR_EN_4 GPIO_ASCR_ASC4
9031#define GPIO_ASCR_EN_5 GPIO_ASCR_ASC5
9032#define GPIO_ASCR_EN_6 GPIO_ASCR_ASC6
9033#define GPIO_ASCR_EN_7 GPIO_ASCR_ASC7
9034#define GPIO_ASCR_EN_8 GPIO_ASCR_ASC8
9035#define GPIO_ASCR_EN_9 GPIO_ASCR_ASC9
9036#define GPIO_ASCR_EN_10 GPIO_ASCR_ASC10
9037#define GPIO_ASCR_EN_11 GPIO_ASCR_ASC11
9038#define GPIO_ASCR_EN_12 GPIO_ASCR_ASC12
9039#define GPIO_ASCR_EN_13 GPIO_ASCR_ASC13
9040#define GPIO_ASCR_EN_14 GPIO_ASCR_ASC14
9041#define GPIO_ASCR_EN_15 GPIO_ASCR_ASC15
9042
9043/******************************************************************************/
9044/* */
9045/* Inter-integrated Circuit Interface (I2C) */
9046/* */
9047/******************************************************************************/
9048/******************* Bit definition for I2C_CR1 register *******************/
9049#define I2C_CR1_PE_Pos (0U)
9050#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9051#define I2C_CR1_PE I2C_CR1_PE_Msk
9052#define I2C_CR1_TXIE_Pos (1U)
9053#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
9054#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
9055#define I2C_CR1_RXIE_Pos (2U)
9056#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
9057#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
9058#define I2C_CR1_ADDRIE_Pos (3U)
9059#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
9060#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
9061#define I2C_CR1_NACKIE_Pos (4U)
9062#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
9063#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
9064#define I2C_CR1_STOPIE_Pos (5U)
9065#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
9066#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
9067#define I2C_CR1_TCIE_Pos (6U)
9068#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
9069#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
9070#define I2C_CR1_ERRIE_Pos (7U)
9071#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
9072#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
9073#define I2C_CR1_DNF_Pos (8U)
9074#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
9075#define I2C_CR1_DNF I2C_CR1_DNF_Msk
9076#define I2C_CR1_ANFOFF_Pos (12U)
9077#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
9078#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
9079#define I2C_CR1_SWRST_Pos (13U)
9080#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
9081#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
9082#define I2C_CR1_TXDMAEN_Pos (14U)
9083#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
9084#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
9085#define I2C_CR1_RXDMAEN_Pos (15U)
9086#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
9087#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
9088#define I2C_CR1_SBC_Pos (16U)
9089#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
9090#define I2C_CR1_SBC I2C_CR1_SBC_Msk
9091#define I2C_CR1_NOSTRETCH_Pos (17U)
9092#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9093#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9094#define I2C_CR1_WUPEN_Pos (18U)
9095#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
9096#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
9097#define I2C_CR1_GCEN_Pos (19U)
9098#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
9099#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
9100#define I2C_CR1_SMBHEN_Pos (20U)
9101#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
9102#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
9103#define I2C_CR1_SMBDEN_Pos (21U)
9104#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
9105#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
9106#define I2C_CR1_ALERTEN_Pos (22U)
9107#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
9108#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
9109#define I2C_CR1_PECEN_Pos (23U)
9110#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
9111#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
9113/****************** Bit definition for I2C_CR2 register ********************/
9114#define I2C_CR2_SADD_Pos (0U)
9115#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
9116#define I2C_CR2_SADD I2C_CR2_SADD_Msk
9117#define I2C_CR2_RD_WRN_Pos (10U)
9118#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
9119#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
9120#define I2C_CR2_ADD10_Pos (11U)
9121#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
9122#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
9123#define I2C_CR2_HEAD10R_Pos (12U)
9124#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
9125#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
9126#define I2C_CR2_START_Pos (13U)
9127#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
9128#define I2C_CR2_START I2C_CR2_START_Msk
9129#define I2C_CR2_STOP_Pos (14U)
9130#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
9131#define I2C_CR2_STOP I2C_CR2_STOP_Msk
9132#define I2C_CR2_NACK_Pos (15U)
9133#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
9134#define I2C_CR2_NACK I2C_CR2_NACK_Msk
9135#define I2C_CR2_NBYTES_Pos (16U)
9136#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
9137#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
9138#define I2C_CR2_RELOAD_Pos (24U)
9139#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
9140#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
9141#define I2C_CR2_AUTOEND_Pos (25U)
9142#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
9143#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
9144#define I2C_CR2_PECBYTE_Pos (26U)
9145#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
9146#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
9148/******************* Bit definition for I2C_OAR1 register ******************/
9149#define I2C_OAR1_OA1_Pos (0U)
9150#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
9151#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
9152#define I2C_OAR1_OA1MODE_Pos (10U)
9153#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
9154#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
9155#define I2C_OAR1_OA1EN_Pos (15U)
9156#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
9157#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
9159/******************* Bit definition for I2C_OAR2 register ******************/
9160#define I2C_OAR2_OA2_Pos (1U)
9161#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
9162#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
9163#define I2C_OAR2_OA2MSK_Pos (8U)
9164#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
9165#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
9166#define I2C_OAR2_OA2NOMASK (0x00000000UL)
9167#define I2C_OAR2_OA2MASK01_Pos (8U)
9168#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
9169#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
9170#define I2C_OAR2_OA2MASK02_Pos (9U)
9171#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
9172#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
9173#define I2C_OAR2_OA2MASK03_Pos (8U)
9174#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
9175#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
9176#define I2C_OAR2_OA2MASK04_Pos (10U)
9177#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
9178#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
9179#define I2C_OAR2_OA2MASK05_Pos (8U)
9180#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
9181#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
9182#define I2C_OAR2_OA2MASK06_Pos (9U)
9183#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
9184#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
9185#define I2C_OAR2_OA2MASK07_Pos (8U)
9186#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
9187#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
9188#define I2C_OAR2_OA2EN_Pos (15U)
9189#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
9190#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
9192/******************* Bit definition for I2C_TIMINGR register *******************/
9193#define I2C_TIMINGR_SCLL_Pos (0U)
9194#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
9195#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
9196#define I2C_TIMINGR_SCLH_Pos (8U)
9197#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
9198#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
9199#define I2C_TIMINGR_SDADEL_Pos (16U)
9200#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
9201#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
9202#define I2C_TIMINGR_SCLDEL_Pos (20U)
9203#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
9204#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
9205#define I2C_TIMINGR_PRESC_Pos (28U)
9206#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
9207#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
9209/******************* Bit definition for I2C_TIMEOUTR register *******************/
9210#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
9211#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
9212#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
9213#define I2C_TIMEOUTR_TIDLE_Pos (12U)
9214#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
9215#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
9216#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
9217#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
9218#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
9219#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
9220#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
9221#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
9222#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
9223#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
9224#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
9226/****************** Bit definition for I2C_ISR register *********************/
9227#define I2C_ISR_TXE_Pos (0U)
9228#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
9229#define I2C_ISR_TXE I2C_ISR_TXE_Msk
9230#define I2C_ISR_TXIS_Pos (1U)
9231#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
9232#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
9233#define I2C_ISR_RXNE_Pos (2U)
9234#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
9235#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
9236#define I2C_ISR_ADDR_Pos (3U)
9237#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
9238#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
9239#define I2C_ISR_NACKF_Pos (4U)
9240#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
9241#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
9242#define I2C_ISR_STOPF_Pos (5U)
9243#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
9244#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
9245#define I2C_ISR_TC_Pos (6U)
9246#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
9247#define I2C_ISR_TC I2C_ISR_TC_Msk
9248#define I2C_ISR_TCR_Pos (7U)
9249#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
9250#define I2C_ISR_TCR I2C_ISR_TCR_Msk
9251#define I2C_ISR_BERR_Pos (8U)
9252#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
9253#define I2C_ISR_BERR I2C_ISR_BERR_Msk
9254#define I2C_ISR_ARLO_Pos (9U)
9255#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
9256#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
9257#define I2C_ISR_OVR_Pos (10U)
9258#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
9259#define I2C_ISR_OVR I2C_ISR_OVR_Msk
9260#define I2C_ISR_PECERR_Pos (11U)
9261#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
9262#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
9263#define I2C_ISR_TIMEOUT_Pos (12U)
9264#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
9265#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
9266#define I2C_ISR_ALERT_Pos (13U)
9267#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
9268#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
9269#define I2C_ISR_BUSY_Pos (15U)
9270#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
9271#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
9272#define I2C_ISR_DIR_Pos (16U)
9273#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
9274#define I2C_ISR_DIR I2C_ISR_DIR_Msk
9275#define I2C_ISR_ADDCODE_Pos (17U)
9276#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
9277#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
9279/****************** Bit definition for I2C_ICR register *********************/
9280#define I2C_ICR_ADDRCF_Pos (3U)
9281#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
9282#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
9283#define I2C_ICR_NACKCF_Pos (4U)
9284#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
9285#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
9286#define I2C_ICR_STOPCF_Pos (5U)
9287#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
9288#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
9289#define I2C_ICR_BERRCF_Pos (8U)
9290#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
9291#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
9292#define I2C_ICR_ARLOCF_Pos (9U)
9293#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
9294#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
9295#define I2C_ICR_OVRCF_Pos (10U)
9296#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
9297#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
9298#define I2C_ICR_PECCF_Pos (11U)
9299#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
9300#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
9301#define I2C_ICR_TIMOUTCF_Pos (12U)
9302#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
9303#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
9304#define I2C_ICR_ALERTCF_Pos (13U)
9305#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
9306#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
9308/****************** Bit definition for I2C_PECR register *********************/
9309#define I2C_PECR_PEC_Pos (0U)
9310#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
9311#define I2C_PECR_PEC I2C_PECR_PEC_Msk
9313/****************** Bit definition for I2C_RXDR register *********************/
9314#define I2C_RXDR_RXDATA_Pos (0U)
9315#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
9316#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
9318/****************** Bit definition for I2C_TXDR register *********************/
9319#define I2C_TXDR_TXDATA_Pos (0U)
9320#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
9321#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
9323/******************************************************************************/
9324/* */
9325/* Independent WATCHDOG */
9326/* */
9327/******************************************************************************/
9328/******************* Bit definition for IWDG_KR register ********************/
9329#define IWDG_KR_KEY_Pos (0U)
9330#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
9331#define IWDG_KR_KEY IWDG_KR_KEY_Msk
9333/******************* Bit definition for IWDG_PR register ********************/
9334#define IWDG_PR_PR_Pos (0U)
9335#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
9336#define IWDG_PR_PR IWDG_PR_PR_Msk
9337#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
9338#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
9339#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
9341/******************* Bit definition for IWDG_RLR register *******************/
9342#define IWDG_RLR_RL_Pos (0U)
9343#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
9344#define IWDG_RLR_RL IWDG_RLR_RL_Msk
9346/******************* Bit definition for IWDG_SR register ********************/
9347#define IWDG_SR_PVU_Pos (0U)
9348#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
9349#define IWDG_SR_PVU IWDG_SR_PVU_Msk
9350#define IWDG_SR_RVU_Pos (1U)
9351#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
9352#define IWDG_SR_RVU IWDG_SR_RVU_Msk
9353#define IWDG_SR_WVU_Pos (2U)
9354#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
9355#define IWDG_SR_WVU IWDG_SR_WVU_Msk
9357/******************* Bit definition for IWDG_KR register ********************/
9358#define IWDG_WINR_WIN_Pos (0U)
9359#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
9360#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
9362/******************************************************************************/
9363/* */
9364/* Firewall */
9365/* */
9366/******************************************************************************/
9367
9368/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
9369#define FW_CSSA_ADD_Pos (8U)
9370#define FW_CSSA_ADD_Msk (0xFFFFUL << FW_CSSA_ADD_Pos)
9371#define FW_CSSA_ADD FW_CSSA_ADD_Msk
9372#define FW_CSL_LENG_Pos (8U)
9373#define FW_CSL_LENG_Msk (0x3FFFUL << FW_CSL_LENG_Pos)
9374#define FW_CSL_LENG FW_CSL_LENG_Msk
9375#define FW_NVDSSA_ADD_Pos (8U)
9376#define FW_NVDSSA_ADD_Msk (0xFFFFUL << FW_NVDSSA_ADD_Pos)
9377#define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk
9378#define FW_NVDSL_LENG_Pos (8U)
9379#define FW_NVDSL_LENG_Msk (0x3FFFUL << FW_NVDSL_LENG_Pos)
9380#define FW_NVDSL_LENG FW_NVDSL_LENG_Msk
9381#define FW_VDSSA_ADD_Pos (6U)
9382#define FW_VDSSA_ADD_Msk (0x7FFUL << FW_VDSSA_ADD_Pos)
9383#define FW_VDSSA_ADD FW_VDSSA_ADD_Msk
9384#define FW_VDSL_LENG_Pos (6U)
9385#define FW_VDSL_LENG_Msk (0x7FFUL << FW_VDSL_LENG_Pos)
9386#define FW_VDSL_LENG FW_VDSL_LENG_Msk
9388/**************************Bit definition for CR register *********************/
9389#define FW_CR_FPA_Pos (0U)
9390#define FW_CR_FPA_Msk (0x1UL << FW_CR_FPA_Pos)
9391#define FW_CR_FPA FW_CR_FPA_Msk
9392#define FW_CR_VDS_Pos (1U)
9393#define FW_CR_VDS_Msk (0x1UL << FW_CR_VDS_Pos)
9394#define FW_CR_VDS FW_CR_VDS_Msk
9395#define FW_CR_VDE_Pos (2U)
9396#define FW_CR_VDE_Msk (0x1UL << FW_CR_VDE_Pos)
9397#define FW_CR_VDE FW_CR_VDE_Msk
9399/******************************************************************************/
9400/* */
9401/* Power Control */
9402/* */
9403/******************************************************************************/
9404
9405/******************** Bit definition for PWR_CR1 register ********************/
9406
9407#define PWR_CR1_LPR_Pos (14U)
9408#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)
9409#define PWR_CR1_LPR PWR_CR1_LPR_Msk
9410#define PWR_CR1_VOS_Pos (9U)
9411#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
9412#define PWR_CR1_VOS PWR_CR1_VOS_Msk
9413#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
9414#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
9415#define PWR_CR1_DBP_Pos (8U)
9416#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
9417#define PWR_CR1_DBP PWR_CR1_DBP_Msk
9418#define PWR_CR1_LPMS_Pos (0U)
9419#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)
9420#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk
9421#define PWR_CR1_LPMS_STOP0 (0x00000000UL)
9422#define PWR_CR1_LPMS_STOP1_Pos (0U)
9423#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos)
9424#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk
9425#define PWR_CR1_LPMS_STOP2_Pos (1U)
9426#define PWR_CR1_LPMS_STOP2_Msk (0x1UL << PWR_CR1_LPMS_STOP2_Pos)
9427#define PWR_CR1_LPMS_STOP2 PWR_CR1_LPMS_STOP2_Msk
9428#define PWR_CR1_LPMS_STANDBY_Pos (0U)
9429#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)
9430#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk
9431#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
9432#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)
9433#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk
9436/******************** Bit definition for PWR_CR2 register ********************/
9437#define PWR_CR2_IOSV_Pos (9U)
9438#define PWR_CR2_IOSV_Msk (0x1UL << PWR_CR2_IOSV_Pos)
9439#define PWR_CR2_IOSV PWR_CR2_IOSV_Msk
9441#define PWR_CR2_PVME_Pos (5U)
9442#define PWR_CR2_PVME_Msk (0x7UL << PWR_CR2_PVME_Pos)
9443#define PWR_CR2_PVME PWR_CR2_PVME_Msk
9444#define PWR_CR2_PVME4_Pos (7U)
9445#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos)
9446#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk
9447#define PWR_CR2_PVME3_Pos (6U)
9448#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos)
9449#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk
9450#define PWR_CR2_PVME2_Pos (5U)
9451#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos)
9452#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk
9454#define PWR_CR2_PLS_Pos (1U)
9455#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos)
9456#define PWR_CR2_PLS PWR_CR2_PLS_Msk
9457#define PWR_CR2_PLS_LEV0 (0x00000000UL)
9458#define PWR_CR2_PLS_LEV1_Pos (1U)
9459#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos)
9460#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk
9461#define PWR_CR2_PLS_LEV2_Pos (2U)
9462#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos)
9463#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk
9464#define PWR_CR2_PLS_LEV3_Pos (1U)
9465#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos)
9466#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk
9467#define PWR_CR2_PLS_LEV4_Pos (3U)
9468#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos)
9469#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk
9470#define PWR_CR2_PLS_LEV5_Pos (1U)
9471#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos)
9472#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk
9473#define PWR_CR2_PLS_LEV6_Pos (2U)
9474#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos)
9475#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk
9476#define PWR_CR2_PLS_LEV7_Pos (1U)
9477#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos)
9478#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk
9479#define PWR_CR2_PVDE_Pos (0U)
9480#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos)
9481#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk
9483/******************** Bit definition for PWR_CR3 register ********************/
9484#define PWR_CR3_EIWUL_Pos (15U)
9485#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos)
9486#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk
9487#define PWR_CR3_APC_Pos (10U)
9488#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)
9489#define PWR_CR3_APC PWR_CR3_APC_Msk
9490#define PWR_CR3_RRS_Pos (8U)
9491#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos)
9492#define PWR_CR3_RRS PWR_CR3_RRS_Msk
9493#define PWR_CR3_EWUP5_Pos (4U)
9494#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos)
9495#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk
9496#define PWR_CR3_EWUP4_Pos (3U)
9497#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)
9498#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk
9499#define PWR_CR3_EWUP3_Pos (2U)
9500#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos)
9501#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk
9502#define PWR_CR3_EWUP2_Pos (1U)
9503#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)
9504#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk
9505#define PWR_CR3_EWUP1_Pos (0U)
9506#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)
9507#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk
9508#define PWR_CR3_EWUP_Pos (0U)
9509#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos)
9510#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk
9512/* Legacy defines */
9513#define PWR_CR3_EIWF_Pos PWR_CR3_EIWUL_Pos
9514#define PWR_CR3_EIWF_Msk PWR_CR3_EIWUL_Msk
9515#define PWR_CR3_EIWF PWR_CR3_EIWUL
9516
9517
9518/******************** Bit definition for PWR_CR4 register ********************/
9519#define PWR_CR4_VBRS_Pos (9U)
9520#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)
9521#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk
9522#define PWR_CR4_VBE_Pos (8U)
9523#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)
9524#define PWR_CR4_VBE PWR_CR4_VBE_Msk
9525#define PWR_CR4_WP5_Pos (4U)
9526#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos)
9527#define PWR_CR4_WP5 PWR_CR4_WP5_Msk
9528#define PWR_CR4_WP4_Pos (3U)
9529#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)
9530#define PWR_CR4_WP4 PWR_CR4_WP4_Msk
9531#define PWR_CR4_WP3_Pos (2U)
9532#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos)
9533#define PWR_CR4_WP3 PWR_CR4_WP3_Msk
9534#define PWR_CR4_WP2_Pos (1U)
9535#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)
9536#define PWR_CR4_WP2 PWR_CR4_WP2_Msk
9537#define PWR_CR4_WP1_Pos (0U)
9538#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)
9539#define PWR_CR4_WP1 PWR_CR4_WP1_Msk
9541/******************** Bit definition for PWR_SR1 register ********************/
9542#define PWR_SR1_WUFI_Pos (15U)
9543#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)
9544#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk
9545#define PWR_SR1_SBF_Pos (8U)
9546#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)
9547#define PWR_SR1_SBF PWR_SR1_SBF_Msk
9548#define PWR_SR1_WUF_Pos (0U)
9549#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos)
9550#define PWR_SR1_WUF PWR_SR1_WUF_Msk
9551#define PWR_SR1_WUF5_Pos (4U)
9552#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos)
9553#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk
9554#define PWR_SR1_WUF4_Pos (3U)
9555#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)
9556#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk
9557#define PWR_SR1_WUF3_Pos (2U)
9558#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos)
9559#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk
9560#define PWR_SR1_WUF2_Pos (1U)
9561#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)
9562#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk
9563#define PWR_SR1_WUF1_Pos (0U)
9564#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)
9565#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk
9567/******************** Bit definition for PWR_SR2 register ********************/
9568#define PWR_SR2_PVMO4_Pos (15U)
9569#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos)
9570#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk
9571#define PWR_SR2_PVMO3_Pos (14U)
9572#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos)
9573#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk
9574#define PWR_SR2_PVMO2_Pos (13U)
9575#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos)
9576#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk
9577#define PWR_SR2_PVDO_Pos (11U)
9578#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos)
9579#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk
9580#define PWR_SR2_VOSF_Pos (10U)
9581#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)
9582#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk
9583#define PWR_SR2_REGLPF_Pos (9U)
9584#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)
9585#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk
9586#define PWR_SR2_REGLPS_Pos (8U)
9587#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)
9588#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk
9590/******************** Bit definition for PWR_SCR register ********************/
9591#define PWR_SCR_CSBF_Pos (8U)
9592#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)
9593#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk
9594#define PWR_SCR_CWUF_Pos (0U)
9595#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos)
9596#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk
9597#define PWR_SCR_CWUF5_Pos (4U)
9598#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos)
9599#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk
9600#define PWR_SCR_CWUF4_Pos (3U)
9601#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)
9602#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk
9603#define PWR_SCR_CWUF3_Pos (2U)
9604#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos)
9605#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk
9606#define PWR_SCR_CWUF2_Pos (1U)
9607#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)
9608#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk
9609#define PWR_SCR_CWUF1_Pos (0U)
9610#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)
9611#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk
9613/******************** Bit definition for PWR_PUCRA register ********************/
9614#define PWR_PUCRA_PA15_Pos (15U)
9615#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos)
9616#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk
9617#define PWR_PUCRA_PA13_Pos (13U)
9618#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos)
9619#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk
9620#define PWR_PUCRA_PA12_Pos (12U)
9621#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos)
9622#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk
9623#define PWR_PUCRA_PA11_Pos (11U)
9624#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos)
9625#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk
9626#define PWR_PUCRA_PA10_Pos (10U)
9627#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos)
9628#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk
9629#define PWR_PUCRA_PA9_Pos (9U)
9630#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos)
9631#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk
9632#define PWR_PUCRA_PA8_Pos (8U)
9633#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos)
9634#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk
9635#define PWR_PUCRA_PA7_Pos (7U)
9636#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos)
9637#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk
9638#define PWR_PUCRA_PA6_Pos (6U)
9639#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos)
9640#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk
9641#define PWR_PUCRA_PA5_Pos (5U)
9642#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos)
9643#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk
9644#define PWR_PUCRA_PA4_Pos (4U)
9645#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos)
9646#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk
9647#define PWR_PUCRA_PA3_Pos (3U)
9648#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos)
9649#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk
9650#define PWR_PUCRA_PA2_Pos (2U)
9651#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos)
9652#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk
9653#define PWR_PUCRA_PA1_Pos (1U)
9654#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos)
9655#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk
9656#define PWR_PUCRA_PA0_Pos (0U)
9657#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos)
9658#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk
9660/******************** Bit definition for PWR_PDCRA register ********************/
9661#define PWR_PDCRA_PA14_Pos (14U)
9662#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos)
9663#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk
9664#define PWR_PDCRA_PA12_Pos (12U)
9665#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos)
9666#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk
9667#define PWR_PDCRA_PA11_Pos (11U)
9668#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos)
9669#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk
9670#define PWR_PDCRA_PA10_Pos (10U)
9671#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos)
9672#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk
9673#define PWR_PDCRA_PA9_Pos (9U)
9674#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos)
9675#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk
9676#define PWR_PDCRA_PA8_Pos (8U)
9677#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos)
9678#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk
9679#define PWR_PDCRA_PA7_Pos (7U)
9680#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos)
9681#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk
9682#define PWR_PDCRA_PA6_Pos (6U)
9683#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos)
9684#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk
9685#define PWR_PDCRA_PA5_Pos (5U)
9686#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos)
9687#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk
9688#define PWR_PDCRA_PA4_Pos (4U)
9689#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos)
9690#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk
9691#define PWR_PDCRA_PA3_Pos (3U)
9692#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos)
9693#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk
9694#define PWR_PDCRA_PA2_Pos (2U)
9695#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos)
9696#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk
9697#define PWR_PDCRA_PA1_Pos (1U)
9698#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos)
9699#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk
9700#define PWR_PDCRA_PA0_Pos (0U)
9701#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos)
9702#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk
9704/******************** Bit definition for PWR_PUCRB register ********************/
9705#define PWR_PUCRB_PB15_Pos (15U)
9706#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos)
9707#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk
9708#define PWR_PUCRB_PB14_Pos (14U)
9709#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos)
9710#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk
9711#define PWR_PUCRB_PB13_Pos (13U)
9712#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos)
9713#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk
9714#define PWR_PUCRB_PB12_Pos (12U)
9715#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos)
9716#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk
9717#define PWR_PUCRB_PB11_Pos (11U)
9718#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos)
9719#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk
9720#define PWR_PUCRB_PB10_Pos (10U)
9721#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos)
9722#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk
9723#define PWR_PUCRB_PB9_Pos (9U)
9724#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos)
9725#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk
9726#define PWR_PUCRB_PB8_Pos (8U)
9727#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos)
9728#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk
9729#define PWR_PUCRB_PB7_Pos (7U)
9730#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos)
9731#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk
9732#define PWR_PUCRB_PB6_Pos (6U)
9733#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos)
9734#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk
9735#define PWR_PUCRB_PB5_Pos (5U)
9736#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos)
9737#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk
9738#define PWR_PUCRB_PB4_Pos (4U)
9739#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos)
9740#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk
9741#define PWR_PUCRB_PB3_Pos (3U)
9742#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos)
9743#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk
9744#define PWR_PUCRB_PB2_Pos (2U)
9745#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos)
9746#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk
9747#define PWR_PUCRB_PB1_Pos (1U)
9748#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos)
9749#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk
9750#define PWR_PUCRB_PB0_Pos (0U)
9751#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos)
9752#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk
9754/******************** Bit definition for PWR_PDCRB register ********************/
9755#define PWR_PDCRB_PB15_Pos (15U)
9756#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos)
9757#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk
9758#define PWR_PDCRB_PB14_Pos (14U)
9759#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos)
9760#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk
9761#define PWR_PDCRB_PB13_Pos (13U)
9762#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos)
9763#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk
9764#define PWR_PDCRB_PB12_Pos (12U)
9765#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos)
9766#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk
9767#define PWR_PDCRB_PB11_Pos (11U)
9768#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos)
9769#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk
9770#define PWR_PDCRB_PB10_Pos (10U)
9771#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos)
9772#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk
9773#define PWR_PDCRB_PB9_Pos (9U)
9774#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos)
9775#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk
9776#define PWR_PDCRB_PB8_Pos (8U)
9777#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos)
9778#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk
9779#define PWR_PDCRB_PB7_Pos (7U)
9780#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos)
9781#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk
9782#define PWR_PDCRB_PB6_Pos (6U)
9783#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos)
9784#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk
9785#define PWR_PDCRB_PB5_Pos (5U)
9786#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos)
9787#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk
9788#define PWR_PDCRB_PB3_Pos (3U)
9789#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos)
9790#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk
9791#define PWR_PDCRB_PB2_Pos (2U)
9792#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos)
9793#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk
9794#define PWR_PDCRB_PB1_Pos (1U)
9795#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos)
9796#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk
9797#define PWR_PDCRB_PB0_Pos (0U)
9798#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos)
9799#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk
9801/******************** Bit definition for PWR_PUCRC register ********************/
9802#define PWR_PUCRC_PC15_Pos (15U)
9803#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos)
9804#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk
9805#define PWR_PUCRC_PC14_Pos (14U)
9806#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos)
9807#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk
9808#define PWR_PUCRC_PC13_Pos (13U)
9809#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos)
9810#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk
9811#define PWR_PUCRC_PC12_Pos (12U)
9812#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos)
9813#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk
9814#define PWR_PUCRC_PC11_Pos (11U)
9815#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos)
9816#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk
9817#define PWR_PUCRC_PC10_Pos (10U)
9818#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos)
9819#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk
9820#define PWR_PUCRC_PC9_Pos (9U)
9821#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos)
9822#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk
9823#define PWR_PUCRC_PC8_Pos (8U)
9824#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos)
9825#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk
9826#define PWR_PUCRC_PC7_Pos (7U)
9827#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos)
9828#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk
9829#define PWR_PUCRC_PC6_Pos (6U)
9830#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos)
9831#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk
9832#define PWR_PUCRC_PC5_Pos (5U)
9833#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos)
9834#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk
9835#define PWR_PUCRC_PC4_Pos (4U)
9836#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos)
9837#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk
9838#define PWR_PUCRC_PC3_Pos (3U)
9839#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos)
9840#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk
9841#define PWR_PUCRC_PC2_Pos (2U)
9842#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos)
9843#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk
9844#define PWR_PUCRC_PC1_Pos (1U)
9845#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos)
9846#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk
9847#define PWR_PUCRC_PC0_Pos (0U)
9848#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos)
9849#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk
9851/******************** Bit definition for PWR_PDCRC register ********************/
9852#define PWR_PDCRC_PC15_Pos (15U)
9853#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos)
9854#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk
9855#define PWR_PDCRC_PC14_Pos (14U)
9856#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos)
9857#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk
9858#define PWR_PDCRC_PC13_Pos (13U)
9859#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos)
9860#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk
9861#define PWR_PDCRC_PC12_Pos (12U)
9862#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos)
9863#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk
9864#define PWR_PDCRC_PC11_Pos (11U)
9865#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos)
9866#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk
9867#define PWR_PDCRC_PC10_Pos (10U)
9868#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos)
9869#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk
9870#define PWR_PDCRC_PC9_Pos (9U)
9871#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos)
9872#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk
9873#define PWR_PDCRC_PC8_Pos (8U)
9874#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos)
9875#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk
9876#define PWR_PDCRC_PC7_Pos (7U)
9877#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos)
9878#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk
9879#define PWR_PDCRC_PC6_Pos (6U)
9880#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos)
9881#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk
9882#define PWR_PDCRC_PC5_Pos (5U)
9883#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos)
9884#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk
9885#define PWR_PDCRC_PC4_Pos (4U)
9886#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos)
9887#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk
9888#define PWR_PDCRC_PC3_Pos (3U)
9889#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos)
9890#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk
9891#define PWR_PDCRC_PC2_Pos (2U)
9892#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos)
9893#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk
9894#define PWR_PDCRC_PC1_Pos (1U)
9895#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos)
9896#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk
9897#define PWR_PDCRC_PC0_Pos (0U)
9898#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos)
9899#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk
9901/******************** Bit definition for PWR_PUCRD register ********************/
9902#define PWR_PUCRD_PD15_Pos (15U)
9903#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos)
9904#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk
9905#define PWR_PUCRD_PD14_Pos (14U)
9906#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos)
9907#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk
9908#define PWR_PUCRD_PD13_Pos (13U)
9909#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos)
9910#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk
9911#define PWR_PUCRD_PD12_Pos (12U)
9912#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos)
9913#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk
9914#define PWR_PUCRD_PD11_Pos (11U)
9915#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos)
9916#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk
9917#define PWR_PUCRD_PD10_Pos (10U)
9918#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos)
9919#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk
9920#define PWR_PUCRD_PD9_Pos (9U)
9921#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos)
9922#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk
9923#define PWR_PUCRD_PD8_Pos (8U)
9924#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos)
9925#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk
9926#define PWR_PUCRD_PD7_Pos (7U)
9927#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos)
9928#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk
9929#define PWR_PUCRD_PD6_Pos (6U)
9930#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos)
9931#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk
9932#define PWR_PUCRD_PD5_Pos (5U)
9933#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos)
9934#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk
9935#define PWR_PUCRD_PD4_Pos (4U)
9936#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos)
9937#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk
9938#define PWR_PUCRD_PD3_Pos (3U)
9939#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos)
9940#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk
9941#define PWR_PUCRD_PD2_Pos (2U)
9942#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos)
9943#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk
9944#define PWR_PUCRD_PD1_Pos (1U)
9945#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos)
9946#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk
9947#define PWR_PUCRD_PD0_Pos (0U)
9948#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos)
9949#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk
9951/******************** Bit definition for PWR_PDCRD register ********************/
9952#define PWR_PDCRD_PD15_Pos (15U)
9953#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos)
9954#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk
9955#define PWR_PDCRD_PD14_Pos (14U)
9956#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos)
9957#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk
9958#define PWR_PDCRD_PD13_Pos (13U)
9959#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos)
9960#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk
9961#define PWR_PDCRD_PD12_Pos (12U)
9962#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos)
9963#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk
9964#define PWR_PDCRD_PD11_Pos (11U)
9965#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos)
9966#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk
9967#define PWR_PDCRD_PD10_Pos (10U)
9968#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos)
9969#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk
9970#define PWR_PDCRD_PD9_Pos (9U)
9971#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos)
9972#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk
9973#define PWR_PDCRD_PD8_Pos (8U)
9974#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos)
9975#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk
9976#define PWR_PDCRD_PD7_Pos (7U)
9977#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos)
9978#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk
9979#define PWR_PDCRD_PD6_Pos (6U)
9980#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos)
9981#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk
9982#define PWR_PDCRD_PD5_Pos (5U)
9983#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos)
9984#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk
9985#define PWR_PDCRD_PD4_Pos (4U)
9986#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos)
9987#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk
9988#define PWR_PDCRD_PD3_Pos (3U)
9989#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)
9990#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk
9991#define PWR_PDCRD_PD2_Pos (2U)
9992#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)
9993#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk
9994#define PWR_PDCRD_PD1_Pos (1U)
9995#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)
9996#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk
9997#define PWR_PDCRD_PD0_Pos (0U)
9998#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)
9999#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk
10001/******************** Bit definition for PWR_PUCRE register ********************/
10002#define PWR_PUCRE_PE15_Pos (15U)
10003#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos)
10004#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk
10005#define PWR_PUCRE_PE14_Pos (14U)
10006#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos)
10007#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk
10008#define PWR_PUCRE_PE13_Pos (13U)
10009#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos)
10010#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk
10011#define PWR_PUCRE_PE12_Pos (12U)
10012#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos)
10013#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk
10014#define PWR_PUCRE_PE11_Pos (11U)
10015#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos)
10016#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk
10017#define PWR_PUCRE_PE10_Pos (10U)
10018#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos)
10019#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk
10020#define PWR_PUCRE_PE9_Pos (9U)
10021#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos)
10022#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk
10023#define PWR_PUCRE_PE8_Pos (8U)
10024#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos)
10025#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk
10026#define PWR_PUCRE_PE7_Pos (7U)
10027#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos)
10028#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk
10029#define PWR_PUCRE_PE6_Pos (6U)
10030#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos)
10031#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk
10032#define PWR_PUCRE_PE5_Pos (5U)
10033#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos)
10034#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk
10035#define PWR_PUCRE_PE4_Pos (4U)
10036#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos)
10037#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk
10038#define PWR_PUCRE_PE3_Pos (3U)
10039#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos)
10040#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk
10041#define PWR_PUCRE_PE2_Pos (2U)
10042#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos)
10043#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk
10044#define PWR_PUCRE_PE1_Pos (1U)
10045#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos)
10046#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk
10047#define PWR_PUCRE_PE0_Pos (0U)
10048#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos)
10049#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk
10051/******************** Bit definition for PWR_PDCRE register ********************/
10052#define PWR_PDCRE_PE15_Pos (15U)
10053#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos)
10054#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk
10055#define PWR_PDCRE_PE14_Pos (14U)
10056#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos)
10057#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk
10058#define PWR_PDCRE_PE13_Pos (13U)
10059#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos)
10060#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk
10061#define PWR_PDCRE_PE12_Pos (12U)
10062#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos)
10063#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk
10064#define PWR_PDCRE_PE11_Pos (11U)
10065#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos)
10066#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk
10067#define PWR_PDCRE_PE10_Pos (10U)
10068#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos)
10069#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk
10070#define PWR_PDCRE_PE9_Pos (9U)
10071#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos)
10072#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk
10073#define PWR_PDCRE_PE8_Pos (8U)
10074#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos)
10075#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk
10076#define PWR_PDCRE_PE7_Pos (7U)
10077#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos)
10078#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk
10079#define PWR_PDCRE_PE6_Pos (6U)
10080#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos)
10081#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk
10082#define PWR_PDCRE_PE5_Pos (5U)
10083#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos)
10084#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk
10085#define PWR_PDCRE_PE4_Pos (4U)
10086#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos)
10087#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk
10088#define PWR_PDCRE_PE3_Pos (3U)
10089#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos)
10090#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk
10091#define PWR_PDCRE_PE2_Pos (2U)
10092#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos)
10093#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk
10094#define PWR_PDCRE_PE1_Pos (1U)
10095#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos)
10096#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk
10097#define PWR_PDCRE_PE0_Pos (0U)
10098#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos)
10099#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk
10101/******************** Bit definition for PWR_PUCRF register ********************/
10102#define PWR_PUCRF_PF15_Pos (15U)
10103#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos)
10104#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk
10105#define PWR_PUCRF_PF14_Pos (14U)
10106#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos)
10107#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk
10108#define PWR_PUCRF_PF13_Pos (13U)
10109#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos)
10110#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk
10111#define PWR_PUCRF_PF12_Pos (12U)
10112#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos)
10113#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk
10114#define PWR_PUCRF_PF11_Pos (11U)
10115#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos)
10116#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk
10117#define PWR_PUCRF_PF10_Pos (10U)
10118#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos)
10119#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk
10120#define PWR_PUCRF_PF9_Pos (9U)
10121#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos)
10122#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk
10123#define PWR_PUCRF_PF8_Pos (8U)
10124#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos)
10125#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk
10126#define PWR_PUCRF_PF7_Pos (7U)
10127#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos)
10128#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk
10129#define PWR_PUCRF_PF6_Pos (6U)
10130#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos)
10131#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk
10132#define PWR_PUCRF_PF5_Pos (5U)
10133#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos)
10134#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk
10135#define PWR_PUCRF_PF4_Pos (4U)
10136#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos)
10137#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk
10138#define PWR_PUCRF_PF3_Pos (3U)
10139#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos)
10140#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk
10141#define PWR_PUCRF_PF2_Pos (2U)
10142#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos)
10143#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk
10144#define PWR_PUCRF_PF1_Pos (1U)
10145#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos)
10146#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk
10147#define PWR_PUCRF_PF0_Pos (0U)
10148#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos)
10149#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk
10151/******************** Bit definition for PWR_PDCRF register ********************/
10152#define PWR_PDCRF_PF15_Pos (15U)
10153#define PWR_PDCRF_PF15_Msk (0x1UL << PWR_PDCRF_PF15_Pos)
10154#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk
10155#define PWR_PDCRF_PF14_Pos (14U)
10156#define PWR_PDCRF_PF14_Msk (0x1UL << PWR_PDCRF_PF14_Pos)
10157#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk
10158#define PWR_PDCRF_PF13_Pos (13U)
10159#define PWR_PDCRF_PF13_Msk (0x1UL << PWR_PDCRF_PF13_Pos)
10160#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk
10161#define PWR_PDCRF_PF12_Pos (12U)
10162#define PWR_PDCRF_PF12_Msk (0x1UL << PWR_PDCRF_PF12_Pos)
10163#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk
10164#define PWR_PDCRF_PF11_Pos (11U)
10165#define PWR_PDCRF_PF11_Msk (0x1UL << PWR_PDCRF_PF11_Pos)
10166#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk
10167#define PWR_PDCRF_PF10_Pos (10U)
10168#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos)
10169#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk
10170#define PWR_PDCRF_PF9_Pos (9U)
10171#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos)
10172#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk
10173#define PWR_PDCRF_PF8_Pos (8U)
10174#define PWR_PDCRF_PF8_Msk (0x1UL << PWR_PDCRF_PF8_Pos)
10175#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk
10176#define PWR_PDCRF_PF7_Pos (7U)
10177#define PWR_PDCRF_PF7_Msk (0x1UL << PWR_PDCRF_PF7_Pos)
10178#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk
10179#define PWR_PDCRF_PF6_Pos (6U)
10180#define PWR_PDCRF_PF6_Msk (0x1UL << PWR_PDCRF_PF6_Pos)
10181#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk
10182#define PWR_PDCRF_PF5_Pos (5U)
10183#define PWR_PDCRF_PF5_Msk (0x1UL << PWR_PDCRF_PF5_Pos)
10184#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk
10185#define PWR_PDCRF_PF4_Pos (4U)
10186#define PWR_PDCRF_PF4_Msk (0x1UL << PWR_PDCRF_PF4_Pos)
10187#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk
10188#define PWR_PDCRF_PF3_Pos (3U)
10189#define PWR_PDCRF_PF3_Msk (0x1UL << PWR_PDCRF_PF3_Pos)
10190#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk
10191#define PWR_PDCRF_PF2_Pos (2U)
10192#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos)
10193#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk
10194#define PWR_PDCRF_PF1_Pos (1U)
10195#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos)
10196#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk
10197#define PWR_PDCRF_PF0_Pos (0U)
10198#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos)
10199#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk
10201/******************** Bit definition for PWR_PUCRG register ********************/
10202#define PWR_PUCRG_PG15_Pos (15U)
10203#define PWR_PUCRG_PG15_Msk (0x1UL << PWR_PUCRG_PG15_Pos)
10204#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk
10205#define PWR_PUCRG_PG14_Pos (14U)
10206#define PWR_PUCRG_PG14_Msk (0x1UL << PWR_PUCRG_PG14_Pos)
10207#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk
10208#define PWR_PUCRG_PG13_Pos (13U)
10209#define PWR_PUCRG_PG13_Msk (0x1UL << PWR_PUCRG_PG13_Pos)
10210#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk
10211#define PWR_PUCRG_PG12_Pos (12U)
10212#define PWR_PUCRG_PG12_Msk (0x1UL << PWR_PUCRG_PG12_Pos)
10213#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk
10214#define PWR_PUCRG_PG11_Pos (11U)
10215#define PWR_PUCRG_PG11_Msk (0x1UL << PWR_PUCRG_PG11_Pos)
10216#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk
10217#define PWR_PUCRG_PG10_Pos (10U)
10218#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos)
10219#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk
10220#define PWR_PUCRG_PG9_Pos (9U)
10221#define PWR_PUCRG_PG9_Msk (0x1UL << PWR_PUCRG_PG9_Pos)
10222#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk
10223#define PWR_PUCRG_PG8_Pos (8U)
10224#define PWR_PUCRG_PG8_Msk (0x1UL << PWR_PUCRG_PG8_Pos)
10225#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk
10226#define PWR_PUCRG_PG7_Pos (7U)
10227#define PWR_PUCRG_PG7_Msk (0x1UL << PWR_PUCRG_PG7_Pos)
10228#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk
10229#define PWR_PUCRG_PG6_Pos (6U)
10230#define PWR_PUCRG_PG6_Msk (0x1UL << PWR_PUCRG_PG6_Pos)
10231#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk
10232#define PWR_PUCRG_PG5_Pos (5U)
10233#define PWR_PUCRG_PG5_Msk (0x1UL << PWR_PUCRG_PG5_Pos)
10234#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk
10235#define PWR_PUCRG_PG4_Pos (4U)
10236#define PWR_PUCRG_PG4_Msk (0x1UL << PWR_PUCRG_PG4_Pos)
10237#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk
10238#define PWR_PUCRG_PG3_Pos (3U)
10239#define PWR_PUCRG_PG3_Msk (0x1UL << PWR_PUCRG_PG3_Pos)
10240#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk
10241#define PWR_PUCRG_PG2_Pos (2U)
10242#define PWR_PUCRG_PG2_Msk (0x1UL << PWR_PUCRG_PG2_Pos)
10243#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk
10244#define PWR_PUCRG_PG1_Pos (1U)
10245#define PWR_PUCRG_PG1_Msk (0x1UL << PWR_PUCRG_PG1_Pos)
10246#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk
10247#define PWR_PUCRG_PG0_Pos (0U)
10248#define PWR_PUCRG_PG0_Msk (0x1UL << PWR_PUCRG_PG0_Pos)
10249#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk
10251/******************** Bit definition for PWR_PDCRG register ********************/
10252#define PWR_PDCRG_PG15_Pos (15U)
10253#define PWR_PDCRG_PG15_Msk (0x1UL << PWR_PDCRG_PG15_Pos)
10254#define PWR_PDCRG_PG15 PWR_PDCRG_PG15_Msk
10255#define PWR_PDCRG_PG14_Pos (14U)
10256#define PWR_PDCRG_PG14_Msk (0x1UL << PWR_PDCRG_PG14_Pos)
10257#define PWR_PDCRG_PG14 PWR_PDCRG_PG14_Msk
10258#define PWR_PDCRG_PG13_Pos (13U)
10259#define PWR_PDCRG_PG13_Msk (0x1UL << PWR_PDCRG_PG13_Pos)
10260#define PWR_PDCRG_PG13 PWR_PDCRG_PG13_Msk
10261#define PWR_PDCRG_PG12_Pos (12U)
10262#define PWR_PDCRG_PG12_Msk (0x1UL << PWR_PDCRG_PG12_Pos)
10263#define PWR_PDCRG_PG12 PWR_PDCRG_PG12_Msk
10264#define PWR_PDCRG_PG11_Pos (11U)
10265#define PWR_PDCRG_PG11_Msk (0x1UL << PWR_PDCRG_PG11_Pos)
10266#define PWR_PDCRG_PG11 PWR_PDCRG_PG11_Msk
10267#define PWR_PDCRG_PG10_Pos (10U)
10268#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos)
10269#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk
10270#define PWR_PDCRG_PG9_Pos (9U)
10271#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos)
10272#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk
10273#define PWR_PDCRG_PG8_Pos (8U)
10274#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos)
10275#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk
10276#define PWR_PDCRG_PG7_Pos (7U)
10277#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos)
10278#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk
10279#define PWR_PDCRG_PG6_Pos (6U)
10280#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos)
10281#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk
10282#define PWR_PDCRG_PG5_Pos (5U)
10283#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos)
10284#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk
10285#define PWR_PDCRG_PG4_Pos (4U)
10286#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos)
10287#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk
10288#define PWR_PDCRG_PG3_Pos (3U)
10289#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos)
10290#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk
10291#define PWR_PDCRG_PG2_Pos (2U)
10292#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos)
10293#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk
10294#define PWR_PDCRG_PG1_Pos (1U)
10295#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos)
10296#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk
10297#define PWR_PDCRG_PG0_Pos (0U)
10298#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos)
10299#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk
10301/******************** Bit definition for PWR_PUCRH register ********************/
10302#define PWR_PUCRH_PH1_Pos (1U)
10303#define PWR_PUCRH_PH1_Msk (0x1UL << PWR_PUCRH_PH1_Pos)
10304#define PWR_PUCRH_PH1 PWR_PUCRH_PH1_Msk
10305#define PWR_PUCRH_PH0_Pos (0U)
10306#define PWR_PUCRH_PH0_Msk (0x1UL << PWR_PUCRH_PH0_Pos)
10307#define PWR_PUCRH_PH0 PWR_PUCRH_PH0_Msk
10309/******************** Bit definition for PWR_PDCRH register ********************/
10310#define PWR_PDCRH_PH1_Pos (1U)
10311#define PWR_PDCRH_PH1_Msk (0x1UL << PWR_PDCRH_PH1_Pos)
10312#define PWR_PDCRH_PH1 PWR_PDCRH_PH1_Msk
10313#define PWR_PDCRH_PH0_Pos (0U)
10314#define PWR_PDCRH_PH0_Msk (0x1UL << PWR_PDCRH_PH0_Pos)
10315#define PWR_PDCRH_PH0 PWR_PDCRH_PH0_Msk
10318/******************************************************************************/
10319/* */
10320/* Reset and Clock Control */
10321/* */
10322/******************************************************************************/
10323/*
10324* @brief Specific device feature definitions (not present on all devices in the STM32L4 series)
10325*/
10326#define RCC_PLLSAI1_SUPPORT
10327#define RCC_PLLP_SUPPORT
10328#define RCC_PLLSAI2_SUPPORT
10329
10330/******************** Bit definition for RCC_CR register ********************/
10331#define RCC_CR_MSION_Pos (0U)
10332#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos)
10333#define RCC_CR_MSION RCC_CR_MSION_Msk
10334#define RCC_CR_MSIRDY_Pos (1U)
10335#define RCC_CR_MSIRDY_Msk (0x1UL << RCC_CR_MSIRDY_Pos)
10336#define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk
10337#define RCC_CR_MSIPLLEN_Pos (2U)
10338#define RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos)
10339#define RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk
10340#define RCC_CR_MSIRGSEL_Pos (3U)
10341#define RCC_CR_MSIRGSEL_Msk (0x1UL << RCC_CR_MSIRGSEL_Pos)
10342#define RCC_CR_MSIRGSEL RCC_CR_MSIRGSEL_Msk
10345#define RCC_CR_MSIRANGE_Pos (4U)
10346#define RCC_CR_MSIRANGE_Msk (0xFUL << RCC_CR_MSIRANGE_Pos)
10347#define RCC_CR_MSIRANGE RCC_CR_MSIRANGE_Msk
10348#define RCC_CR_MSIRANGE_0 (0x0UL << RCC_CR_MSIRANGE_Pos)
10349#define RCC_CR_MSIRANGE_1 (0x1UL << RCC_CR_MSIRANGE_Pos)
10350#define RCC_CR_MSIRANGE_2 (0x2UL << RCC_CR_MSIRANGE_Pos)
10351#define RCC_CR_MSIRANGE_3 (0x3UL << RCC_CR_MSIRANGE_Pos)
10352#define RCC_CR_MSIRANGE_4 (0x4UL << RCC_CR_MSIRANGE_Pos)
10353#define RCC_CR_MSIRANGE_5 (0x5UL << RCC_CR_MSIRANGE_Pos)
10354#define RCC_CR_MSIRANGE_6 (0x6UL << RCC_CR_MSIRANGE_Pos)
10355#define RCC_CR_MSIRANGE_7 (0x7UL << RCC_CR_MSIRANGE_Pos)
10356#define RCC_CR_MSIRANGE_8 (0x8UL << RCC_CR_MSIRANGE_Pos)
10357#define RCC_CR_MSIRANGE_9 (0x9UL << RCC_CR_MSIRANGE_Pos)
10358#define RCC_CR_MSIRANGE_10 (0xAUL << RCC_CR_MSIRANGE_Pos)
10359#define RCC_CR_MSIRANGE_11 (0xBUL << RCC_CR_MSIRANGE_Pos)
10361#define RCC_CR_HSION_Pos (8U)
10362#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
10363#define RCC_CR_HSION RCC_CR_HSION_Msk
10364#define RCC_CR_HSIKERON_Pos (9U)
10365#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
10366#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
10367#define RCC_CR_HSIRDY_Pos (10U)
10368#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
10369#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
10370#define RCC_CR_HSIASFS_Pos (11U)
10371#define RCC_CR_HSIASFS_Msk (0x1UL << RCC_CR_HSIASFS_Pos)
10372#define RCC_CR_HSIASFS RCC_CR_HSIASFS_Msk
10374#define RCC_CR_HSEON_Pos (16U)
10375#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
10376#define RCC_CR_HSEON RCC_CR_HSEON_Msk
10377#define RCC_CR_HSERDY_Pos (17U)
10378#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
10379#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
10380#define RCC_CR_HSEBYP_Pos (18U)
10381#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
10382#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
10383#define RCC_CR_CSSON_Pos (19U)
10384#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
10385#define RCC_CR_CSSON RCC_CR_CSSON_Msk
10387#define RCC_CR_PLLON_Pos (24U)
10388#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
10389#define RCC_CR_PLLON RCC_CR_PLLON_Msk
10390#define RCC_CR_PLLRDY_Pos (25U)
10391#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
10392#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
10393#define RCC_CR_PLLSAI1ON_Pos (26U)
10394#define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos)
10395#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk
10396#define RCC_CR_PLLSAI1RDY_Pos (27U)
10397#define RCC_CR_PLLSAI1RDY_Msk (0x1UL << RCC_CR_PLLSAI1RDY_Pos)
10398#define RCC_CR_PLLSAI1RDY RCC_CR_PLLSAI1RDY_Msk
10399#define RCC_CR_PLLSAI2ON_Pos (28U)
10400#define RCC_CR_PLLSAI2ON_Msk (0x1UL << RCC_CR_PLLSAI2ON_Pos)
10401#define RCC_CR_PLLSAI2ON RCC_CR_PLLSAI2ON_Msk
10402#define RCC_CR_PLLSAI2RDY_Pos (29U)
10403#define RCC_CR_PLLSAI2RDY_Msk (0x1UL << RCC_CR_PLLSAI2RDY_Pos)
10404#define RCC_CR_PLLSAI2RDY RCC_CR_PLLSAI2RDY_Msk
10406/******************** Bit definition for RCC_ICSCR register ***************/
10408#define RCC_ICSCR_MSICAL_Pos (0U)
10409#define RCC_ICSCR_MSICAL_Msk (0xFFUL << RCC_ICSCR_MSICAL_Pos)
10410#define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk
10411#define RCC_ICSCR_MSICAL_0 (0x01UL << RCC_ICSCR_MSICAL_Pos)
10412#define RCC_ICSCR_MSICAL_1 (0x02UL << RCC_ICSCR_MSICAL_Pos)
10413#define RCC_ICSCR_MSICAL_2 (0x04UL << RCC_ICSCR_MSICAL_Pos)
10414#define RCC_ICSCR_MSICAL_3 (0x08UL << RCC_ICSCR_MSICAL_Pos)
10415#define RCC_ICSCR_MSICAL_4 (0x10UL << RCC_ICSCR_MSICAL_Pos)
10416#define RCC_ICSCR_MSICAL_5 (0x20UL << RCC_ICSCR_MSICAL_Pos)
10417#define RCC_ICSCR_MSICAL_6 (0x40UL << RCC_ICSCR_MSICAL_Pos)
10418#define RCC_ICSCR_MSICAL_7 (0x80UL << RCC_ICSCR_MSICAL_Pos)
10421#define RCC_ICSCR_MSITRIM_Pos (8U)
10422#define RCC_ICSCR_MSITRIM_Msk (0xFFUL << RCC_ICSCR_MSITRIM_Pos)
10423#define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk
10424#define RCC_ICSCR_MSITRIM_0 (0x01UL << RCC_ICSCR_MSITRIM_Pos)
10425#define RCC_ICSCR_MSITRIM_1 (0x02UL << RCC_ICSCR_MSITRIM_Pos)
10426#define RCC_ICSCR_MSITRIM_2 (0x04UL << RCC_ICSCR_MSITRIM_Pos)
10427#define RCC_ICSCR_MSITRIM_3 (0x08UL << RCC_ICSCR_MSITRIM_Pos)
10428#define RCC_ICSCR_MSITRIM_4 (0x10UL << RCC_ICSCR_MSITRIM_Pos)
10429#define RCC_ICSCR_MSITRIM_5 (0x20UL << RCC_ICSCR_MSITRIM_Pos)
10430#define RCC_ICSCR_MSITRIM_6 (0x40UL << RCC_ICSCR_MSITRIM_Pos)
10431#define RCC_ICSCR_MSITRIM_7 (0x80UL << RCC_ICSCR_MSITRIM_Pos)
10434#define RCC_ICSCR_HSICAL_Pos (16U)
10435#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)
10436#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk
10437#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)
10438#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)
10439#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)
10440#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)
10441#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)
10442#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)
10443#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)
10444#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)
10447#define RCC_ICSCR_HSITRIM_Pos (24U)
10448#define RCC_ICSCR_HSITRIM_Msk (0x1FUL << RCC_ICSCR_HSITRIM_Pos)
10449#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk
10450#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)
10451#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)
10452#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)
10453#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)
10454#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)
10456/******************** Bit definition for RCC_CFGR register ******************/
10458#define RCC_CFGR_SW_Pos (0U)
10459#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
10460#define RCC_CFGR_SW RCC_CFGR_SW_Msk
10461#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
10462#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
10464#define RCC_CFGR_SW_MSI (0x00000000UL)
10465#define RCC_CFGR_SW_HSI (0x00000001UL)
10466#define RCC_CFGR_SW_HSE (0x00000002UL)
10467#define RCC_CFGR_SW_PLL (0x00000003UL)
10470#define RCC_CFGR_SWS_Pos (2U)
10471#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
10472#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
10473#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
10474#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
10476#define RCC_CFGR_SWS_MSI (0x00000000UL)
10477#define RCC_CFGR_SWS_HSI (0x00000004UL)
10478#define RCC_CFGR_SWS_HSE (0x00000008UL)
10479#define RCC_CFGR_SWS_PLL (0x0000000CUL)
10482#define RCC_CFGR_HPRE_Pos (4U)
10483#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
10484#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
10485#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
10486#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
10487#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
10488#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
10490#define RCC_CFGR_HPRE_DIV1 (0x00000000UL)
10491#define RCC_CFGR_HPRE_DIV2 (0x00000080UL)
10492#define RCC_CFGR_HPRE_DIV4 (0x00000090UL)
10493#define RCC_CFGR_HPRE_DIV8 (0x000000A0UL)
10494#define RCC_CFGR_HPRE_DIV16 (0x000000B0UL)
10495#define RCC_CFGR_HPRE_DIV64 (0x000000C0UL)
10496#define RCC_CFGR_HPRE_DIV128 (0x000000D0UL)
10497#define RCC_CFGR_HPRE_DIV256 (0x000000E0UL)
10498#define RCC_CFGR_HPRE_DIV512 (0x000000F0UL)
10501#define RCC_CFGR_PPRE1_Pos (8U)
10502#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
10503#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
10504#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
10505#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
10506#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
10508#define RCC_CFGR_PPRE1_DIV1 (0x00000000UL)
10509#define RCC_CFGR_PPRE1_DIV2 (0x00000400UL)
10510#define RCC_CFGR_PPRE1_DIV4 (0x00000500UL)
10511#define RCC_CFGR_PPRE1_DIV8 (0x00000600UL)
10512#define RCC_CFGR_PPRE1_DIV16 (0x00000700UL)
10515#define RCC_CFGR_PPRE2_Pos (11U)
10516#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
10517#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
10518#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
10519#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
10520#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
10522#define RCC_CFGR_PPRE2_DIV1 (0x00000000UL)
10523#define RCC_CFGR_PPRE2_DIV2 (0x00002000UL)
10524#define RCC_CFGR_PPRE2_DIV4 (0x00002800UL)
10525#define RCC_CFGR_PPRE2_DIV8 (0x00003000UL)
10526#define RCC_CFGR_PPRE2_DIV16 (0x00003800UL)
10528#define RCC_CFGR_STOPWUCK_Pos (15U)
10529#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
10530#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
10533#define RCC_CFGR_MCOSEL_Pos (24U)
10534#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos)
10535#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk
10536#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)
10537#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)
10538#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)
10540#define RCC_CFGR_MCOPRE_Pos (28U)
10541#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)
10542#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk
10543#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)
10544#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)
10545#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)
10547#define RCC_CFGR_MCOPRE_DIV1 (0x00000000UL)
10548#define RCC_CFGR_MCOPRE_DIV2 (0x10000000UL)
10549#define RCC_CFGR_MCOPRE_DIV4 (0x20000000UL)
10550#define RCC_CFGR_MCOPRE_DIV8 (0x30000000UL)
10551#define RCC_CFGR_MCOPRE_DIV16 (0x40000000UL)
10553/* Legacy aliases */
10554#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
10555#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
10556#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
10557#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
10558#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
10559#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
10560
10561/******************** Bit definition for RCC_PLLCFGR register ***************/
10562#define RCC_PLLCFGR_PLLSRC_Pos (0U)
10563#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)
10564#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
10565
10566#define RCC_PLLCFGR_PLLSRC_MSI_Pos (0U)
10567#define RCC_PLLCFGR_PLLSRC_MSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_MSI_Pos)
10568#define RCC_PLLCFGR_PLLSRC_MSI RCC_PLLCFGR_PLLSRC_MSI_Msk
10569#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
10570#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)
10571#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk
10572#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
10573#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
10574#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
10576#define RCC_PLLCFGR_PLLM_Pos (4U)
10577#define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos)
10578#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
10579#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)
10580#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)
10581#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)
10583#define RCC_PLLCFGR_PLLN_Pos (8U)
10584#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)
10585#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
10586#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)
10587#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)
10588#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)
10589#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)
10590#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)
10591#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)
10592#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)
10594#define RCC_PLLCFGR_PLLPEN_Pos (16U)
10595#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)
10596#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
10597#define RCC_PLLCFGR_PLLP_Pos (17U)
10598#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos)
10599#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
10600#define RCC_PLLCFGR_PLLQEN_Pos (20U)
10601#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)
10602#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
10603
10604#define RCC_PLLCFGR_PLLQ_Pos (21U)
10605#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos)
10606#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
10607#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
10608#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
10610#define RCC_PLLCFGR_PLLREN_Pos (24U)
10611#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)
10612#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
10613#define RCC_PLLCFGR_PLLR_Pos (25U)
10614#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos)
10615#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
10616#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
10617#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
10619/******************** Bit definition for RCC_PLLSAI1CFGR register ************/
10620#define RCC_PLLSAI1CFGR_PLLSAI1N_Pos (8U)
10621#define RCC_PLLSAI1CFGR_PLLSAI1N_Msk (0x7FUL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10622#define RCC_PLLSAI1CFGR_PLLSAI1N RCC_PLLSAI1CFGR_PLLSAI1N_Msk
10623#define RCC_PLLSAI1CFGR_PLLSAI1N_0 (0x01UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10624#define RCC_PLLSAI1CFGR_PLLSAI1N_1 (0x02UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10625#define RCC_PLLSAI1CFGR_PLLSAI1N_2 (0x04UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10626#define RCC_PLLSAI1CFGR_PLLSAI1N_3 (0x08UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10627#define RCC_PLLSAI1CFGR_PLLSAI1N_4 (0x10UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10628#define RCC_PLLSAI1CFGR_PLLSAI1N_5 (0x20UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10629#define RCC_PLLSAI1CFGR_PLLSAI1N_6 (0x40UL << RCC_PLLSAI1CFGR_PLLSAI1N_Pos)
10631#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos (16U)
10632#define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos)
10633#define RCC_PLLSAI1CFGR_PLLSAI1PEN RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
10634#define RCC_PLLSAI1CFGR_PLLSAI1P_Pos (17U)
10635#define RCC_PLLSAI1CFGR_PLLSAI1P_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1P_Pos)
10636#define RCC_PLLSAI1CFGR_PLLSAI1P RCC_PLLSAI1CFGR_PLLSAI1P_Msk
10637
10638#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos (20U)
10639#define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos)
10640#define RCC_PLLSAI1CFGR_PLLSAI1QEN RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
10641#define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos (21U)
10642#define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
10643#define RCC_PLLSAI1CFGR_PLLSAI1Q RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
10644#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
10645#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos)
10647#define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos (24U)
10648#define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos)
10649#define RCC_PLLSAI1CFGR_PLLSAI1REN RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
10650#define RCC_PLLSAI1CFGR_PLLSAI1R_Pos (25U)
10651#define RCC_PLLSAI1CFGR_PLLSAI1R_Msk (0x3UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
10652#define RCC_PLLSAI1CFGR_PLLSAI1R RCC_PLLSAI1CFGR_PLLSAI1R_Msk
10653#define RCC_PLLSAI1CFGR_PLLSAI1R_0 (0x1UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
10654#define RCC_PLLSAI1CFGR_PLLSAI1R_1 (0x2UL << RCC_PLLSAI1CFGR_PLLSAI1R_Pos)
10656/******************** Bit definition for RCC_PLLSAI2CFGR register ************/
10657#define RCC_PLLSAI2CFGR_PLLSAI2N_Pos (8U)
10658#define RCC_PLLSAI2CFGR_PLLSAI2N_Msk (0x7FUL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10659#define RCC_PLLSAI2CFGR_PLLSAI2N RCC_PLLSAI2CFGR_PLLSAI2N_Msk
10660#define RCC_PLLSAI2CFGR_PLLSAI2N_0 (0x01UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10661#define RCC_PLLSAI2CFGR_PLLSAI2N_1 (0x02UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10662#define RCC_PLLSAI2CFGR_PLLSAI2N_2 (0x04UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10663#define RCC_PLLSAI2CFGR_PLLSAI2N_3 (0x08UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10664#define RCC_PLLSAI2CFGR_PLLSAI2N_4 (0x10UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10665#define RCC_PLLSAI2CFGR_PLLSAI2N_5 (0x20UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10666#define RCC_PLLSAI2CFGR_PLLSAI2N_6 (0x40UL << RCC_PLLSAI2CFGR_PLLSAI2N_Pos)
10668#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos (16U)
10669#define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos)
10670#define RCC_PLLSAI2CFGR_PLLSAI2PEN RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
10671#define RCC_PLLSAI2CFGR_PLLSAI2P_Pos (17U)
10672#define RCC_PLLSAI2CFGR_PLLSAI2P_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2P_Pos)
10673#define RCC_PLLSAI2CFGR_PLLSAI2P RCC_PLLSAI2CFGR_PLLSAI2P_Msk
10674
10675#define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos (24U)
10676#define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos)
10677#define RCC_PLLSAI2CFGR_PLLSAI2REN RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
10678#define RCC_PLLSAI2CFGR_PLLSAI2R_Pos (25U)
10679#define RCC_PLLSAI2CFGR_PLLSAI2R_Msk (0x3UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
10680#define RCC_PLLSAI2CFGR_PLLSAI2R RCC_PLLSAI2CFGR_PLLSAI2R_Msk
10681#define RCC_PLLSAI2CFGR_PLLSAI2R_0 (0x1UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
10682#define RCC_PLLSAI2CFGR_PLLSAI2R_1 (0x2UL << RCC_PLLSAI2CFGR_PLLSAI2R_Pos)
10684/******************** Bit definition for RCC_CIER register ******************/
10685#define RCC_CIER_LSIRDYIE_Pos (0U)
10686#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
10687#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
10688#define RCC_CIER_LSERDYIE_Pos (1U)
10689#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
10690#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
10691#define RCC_CIER_MSIRDYIE_Pos (2U)
10692#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos)
10693#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk
10694#define RCC_CIER_HSIRDYIE_Pos (3U)
10695#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
10696#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
10697#define RCC_CIER_HSERDYIE_Pos (4U)
10698#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
10699#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
10700#define RCC_CIER_PLLRDYIE_Pos (5U)
10701#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)
10702#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
10703#define RCC_CIER_PLLSAI1RDYIE_Pos (6U)
10704#define RCC_CIER_PLLSAI1RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI1RDYIE_Pos)
10705#define RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE_Msk
10706#define RCC_CIER_PLLSAI2RDYIE_Pos (7U)
10707#define RCC_CIER_PLLSAI2RDYIE_Msk (0x1UL << RCC_CIER_PLLSAI2RDYIE_Pos)
10708#define RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE_Msk
10709#define RCC_CIER_LSECSSIE_Pos (9U)
10710#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
10711#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
10712
10713/******************** Bit definition for RCC_CIFR register ******************/
10714#define RCC_CIFR_LSIRDYF_Pos (0U)
10715#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
10716#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
10717#define RCC_CIFR_LSERDYF_Pos (1U)
10718#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
10719#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
10720#define RCC_CIFR_MSIRDYF_Pos (2U)
10721#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos)
10722#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk
10723#define RCC_CIFR_HSIRDYF_Pos (3U)
10724#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
10725#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
10726#define RCC_CIFR_HSERDYF_Pos (4U)
10727#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
10728#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
10729#define RCC_CIFR_PLLRDYF_Pos (5U)
10730#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
10731#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
10732#define RCC_CIFR_PLLSAI1RDYF_Pos (6U)
10733#define RCC_CIFR_PLLSAI1RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI1RDYF_Pos)
10734#define RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF_Msk
10735#define RCC_CIFR_PLLSAI2RDYF_Pos (7U)
10736#define RCC_CIFR_PLLSAI2RDYF_Msk (0x1UL << RCC_CIFR_PLLSAI2RDYF_Pos)
10737#define RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF_Msk
10738#define RCC_CIFR_CSSF_Pos (8U)
10739#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)
10740#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
10741#define RCC_CIFR_LSECSSF_Pos (9U)
10742#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
10743#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
10744
10745/******************** Bit definition for RCC_CICR register ******************/
10746#define RCC_CICR_LSIRDYC_Pos (0U)
10747#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
10748#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
10749#define RCC_CICR_LSERDYC_Pos (1U)
10750#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
10751#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
10752#define RCC_CICR_MSIRDYC_Pos (2U)
10753#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos)
10754#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk
10755#define RCC_CICR_HSIRDYC_Pos (3U)
10756#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
10757#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
10758#define RCC_CICR_HSERDYC_Pos (4U)
10759#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
10760#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
10761#define RCC_CICR_PLLRDYC_Pos (5U)
10762#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
10763#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
10764#define RCC_CICR_PLLSAI1RDYC_Pos (6U)
10765#define RCC_CICR_PLLSAI1RDYC_Msk (0x1UL << RCC_CICR_PLLSAI1RDYC_Pos)
10766#define RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC_Msk
10767#define RCC_CICR_PLLSAI2RDYC_Pos (7U)
10768#define RCC_CICR_PLLSAI2RDYC_Msk (0x1UL << RCC_CICR_PLLSAI2RDYC_Pos)
10769#define RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC_Msk
10770#define RCC_CICR_CSSC_Pos (8U)
10771#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)
10772#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
10773#define RCC_CICR_LSECSSC_Pos (9U)
10774#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
10775#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
10776
10777/******************** Bit definition for RCC_AHB1RSTR register **************/
10778#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
10779#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
10780#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
10781#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
10782#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
10783#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
10784#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
10785#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)
10786#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
10787#define RCC_AHB1RSTR_CRCRST_Pos (12U)
10788#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
10789#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
10790#define RCC_AHB1RSTR_TSCRST_Pos (16U)
10791#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos)
10792#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk
10793
10794/******************** Bit definition for RCC_AHB2RSTR register **************/
10795#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
10796#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)
10797#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
10798#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
10799#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)
10800#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
10801#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
10802#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)
10803#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
10804#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
10805#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)
10806#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
10807#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
10808#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)
10809#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
10810#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
10811#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)
10812#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
10813#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
10814#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)
10815#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
10816#define RCC_AHB2RSTR_GPIOHRST_Pos (7U)
10817#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)
10818#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk
10819#define RCC_AHB2RSTR_OTGFSRST_Pos (12U)
10820#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
10821#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
10822#define RCC_AHB2RSTR_ADCRST_Pos (13U)
10823#define RCC_AHB2RSTR_ADCRST_Msk (0x1UL << RCC_AHB2RSTR_ADCRST_Pos)
10824#define RCC_AHB2RSTR_ADCRST RCC_AHB2RSTR_ADCRST_Msk
10825#define RCC_AHB2RSTR_RNGRST_Pos (18U)
10826#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
10827#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
10828
10829/******************** Bit definition for RCC_AHB3RSTR register **************/
10830#define RCC_AHB3RSTR_FMCRST_Pos (0U)
10831#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
10832#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
10833#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
10834#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
10835#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
10836
10837/******************** Bit definition for RCC_APB1RSTR1 register **************/
10838#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
10839#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)
10840#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
10841#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
10842#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)
10843#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
10844#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
10845#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)
10846#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
10847#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
10848#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)
10849#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
10850#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
10851#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)
10852#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
10853#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
10854#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)
10855#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
10856#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
10857#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)
10858#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
10859#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
10860#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)
10861#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
10862#define RCC_APB1RSTR1_USART2RST_Pos (17U)
10863#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)
10864#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
10865#define RCC_APB1RSTR1_USART3RST_Pos (18U)
10866#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)
10867#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
10868#define RCC_APB1RSTR1_UART4RST_Pos (19U)
10869#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)
10870#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
10871#define RCC_APB1RSTR1_UART5RST_Pos (20U)
10872#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)
10873#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
10874#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
10875#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)
10876#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
10877#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
10878#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)
10879#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
10880#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
10881#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)
10882#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
10883#define RCC_APB1RSTR1_CAN1RST_Pos (25U)
10884#define RCC_APB1RSTR1_CAN1RST_Msk (0x1UL << RCC_APB1RSTR1_CAN1RST_Pos)
10885#define RCC_APB1RSTR1_CAN1RST RCC_APB1RSTR1_CAN1RST_Msk
10886#define RCC_APB1RSTR1_PWRRST_Pos (28U)
10887#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)
10888#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
10889#define RCC_APB1RSTR1_DAC1RST_Pos (29U)
10890#define RCC_APB1RSTR1_DAC1RST_Msk (0x1UL << RCC_APB1RSTR1_DAC1RST_Pos)
10891#define RCC_APB1RSTR1_DAC1RST RCC_APB1RSTR1_DAC1RST_Msk
10892#define RCC_APB1RSTR1_OPAMPRST_Pos (30U)
10893#define RCC_APB1RSTR1_OPAMPRST_Msk (0x1UL << RCC_APB1RSTR1_OPAMPRST_Pos)
10894#define RCC_APB1RSTR1_OPAMPRST RCC_APB1RSTR1_OPAMPRST_Msk
10895#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
10896#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)
10897#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
10898
10899/******************** Bit definition for RCC_APB1RSTR2 register **************/
10900#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
10901#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)
10902#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
10903#define RCC_APB1RSTR2_SWPMI1RST_Pos (2U)
10904#define RCC_APB1RSTR2_SWPMI1RST_Msk (0x1UL << RCC_APB1RSTR2_SWPMI1RST_Pos)
10905#define RCC_APB1RSTR2_SWPMI1RST RCC_APB1RSTR2_SWPMI1RST_Msk
10906#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U)
10907#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)
10908#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk
10909
10910/******************** Bit definition for RCC_APB2RSTR register **************/
10911#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
10912#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
10913#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
10914#define RCC_APB2RSTR_SDMMC1RST_Pos (10U)
10915#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos)
10916#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
10917#define RCC_APB2RSTR_TIM1RST_Pos (11U)
10918#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
10919#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
10920#define RCC_APB2RSTR_SPI1RST_Pos (12U)
10921#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
10922#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
10923#define RCC_APB2RSTR_TIM8RST_Pos (13U)
10924#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
10925#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
10926#define RCC_APB2RSTR_USART1RST_Pos (14U)
10927#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
10928#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
10929#define RCC_APB2RSTR_TIM15RST_Pos (16U)
10930#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
10931#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
10932#define RCC_APB2RSTR_TIM16RST_Pos (17U)
10933#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
10934#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
10935#define RCC_APB2RSTR_TIM17RST_Pos (18U)
10936#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
10937#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
10938#define RCC_APB2RSTR_SAI1RST_Pos (21U)
10939#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
10940#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
10941#define RCC_APB2RSTR_SAI2RST_Pos (22U)
10942#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
10943#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
10944#define RCC_APB2RSTR_DFSDM1RST_Pos (24U)
10945#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
10946#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
10947
10948/******************** Bit definition for RCC_AHB1ENR register ***************/
10949#define RCC_AHB1ENR_DMA1EN_Pos (0U)
10950#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
10951#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
10952#define RCC_AHB1ENR_DMA2EN_Pos (1U)
10953#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
10954#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
10955#define RCC_AHB1ENR_FLASHEN_Pos (8U)
10956#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)
10957#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
10958#define RCC_AHB1ENR_CRCEN_Pos (12U)
10959#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
10960#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
10961#define RCC_AHB1ENR_TSCEN_Pos (16U)
10962#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos)
10963#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk
10964
10965/******************** Bit definition for RCC_AHB2ENR register ***************/
10966#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
10967#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)
10968#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
10969#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
10970#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)
10971#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
10972#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
10973#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)
10974#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
10975#define RCC_AHB2ENR_GPIODEN_Pos (3U)
10976#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)
10977#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
10978#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
10979#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)
10980#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
10981#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
10982#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)
10983#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
10984#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
10985#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)
10986#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
10987#define RCC_AHB2ENR_GPIOHEN_Pos (7U)
10988#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos)
10989#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk
10990#define RCC_AHB2ENR_OTGFSEN_Pos (12U)
10991#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
10992#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
10993#define RCC_AHB2ENR_ADCEN_Pos (13U)
10994#define RCC_AHB2ENR_ADCEN_Msk (0x1UL << RCC_AHB2ENR_ADCEN_Pos)
10995#define RCC_AHB2ENR_ADCEN RCC_AHB2ENR_ADCEN_Msk
10996#define RCC_AHB2ENR_RNGEN_Pos (18U)
10997#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
10998#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
10999
11000/******************** Bit definition for RCC_AHB3ENR register ***************/
11001#define RCC_AHB3ENR_FMCEN_Pos (0U)
11002#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
11003#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
11004#define RCC_AHB3ENR_QSPIEN_Pos (8U)
11005#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
11006#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
11007
11008/******************** Bit definition for RCC_APB1ENR1 register ***************/
11009#define RCC_APB1ENR1_TIM2EN_Pos (0U)
11010#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)
11011#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
11012#define RCC_APB1ENR1_TIM3EN_Pos (1U)
11013#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)
11014#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
11015#define RCC_APB1ENR1_TIM4EN_Pos (2U)
11016#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)
11017#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
11018#define RCC_APB1ENR1_TIM5EN_Pos (3U)
11019#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)
11020#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
11021#define RCC_APB1ENR1_TIM6EN_Pos (4U)
11022#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)
11023#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
11024#define RCC_APB1ENR1_TIM7EN_Pos (5U)
11025#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)
11026#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
11027#define RCC_APB1ENR1_WWDGEN_Pos (11U)
11028#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)
11029#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
11030#define RCC_APB1ENR1_SPI2EN_Pos (14U)
11031#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)
11032#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
11033#define RCC_APB1ENR1_SPI3EN_Pos (15U)
11034#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)
11035#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
11036#define RCC_APB1ENR1_USART2EN_Pos (17U)
11037#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)
11038#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
11039#define RCC_APB1ENR1_USART3EN_Pos (18U)
11040#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)
11041#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
11042#define RCC_APB1ENR1_UART4EN_Pos (19U)
11043#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)
11044#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
11045#define RCC_APB1ENR1_UART5EN_Pos (20U)
11046#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)
11047#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
11048#define RCC_APB1ENR1_I2C1EN_Pos (21U)
11049#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)
11050#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
11051#define RCC_APB1ENR1_I2C2EN_Pos (22U)
11052#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)
11053#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
11054#define RCC_APB1ENR1_I2C3EN_Pos (23U)
11055#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)
11056#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
11057#define RCC_APB1ENR1_CAN1EN_Pos (25U)
11058#define RCC_APB1ENR1_CAN1EN_Msk (0x1UL << RCC_APB1ENR1_CAN1EN_Pos)
11059#define RCC_APB1ENR1_CAN1EN RCC_APB1ENR1_CAN1EN_Msk
11060#define RCC_APB1ENR1_PWREN_Pos (28U)
11061#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos)
11062#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
11063#define RCC_APB1ENR1_DAC1EN_Pos (29U)
11064#define RCC_APB1ENR1_DAC1EN_Msk (0x1UL << RCC_APB1ENR1_DAC1EN_Pos)
11065#define RCC_APB1ENR1_DAC1EN RCC_APB1ENR1_DAC1EN_Msk
11066#define RCC_APB1ENR1_OPAMPEN_Pos (30U)
11067#define RCC_APB1ENR1_OPAMPEN_Msk (0x1UL << RCC_APB1ENR1_OPAMPEN_Pos)
11068#define RCC_APB1ENR1_OPAMPEN RCC_APB1ENR1_OPAMPEN_Msk
11069#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
11070#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)
11071#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
11072
11073/******************** Bit definition for RCC_APB1RSTR2 register **************/
11074#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
11075#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)
11076#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
11077#define RCC_APB1ENR2_SWPMI1EN_Pos (2U)
11078#define RCC_APB1ENR2_SWPMI1EN_Msk (0x1UL << RCC_APB1ENR2_SWPMI1EN_Pos)
11079#define RCC_APB1ENR2_SWPMI1EN RCC_APB1ENR2_SWPMI1EN_Msk
11080#define RCC_APB1ENR2_LPTIM2EN_Pos (5U)
11081#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)
11082#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk
11083
11084/******************** Bit definition for RCC_APB2ENR register ***************/
11085#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
11086#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
11087#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
11088#define RCC_APB2ENR_FWEN_Pos (7U)
11089#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos)
11090#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk
11091#define RCC_APB2ENR_SDMMC1EN_Pos (10U)
11092#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)
11093#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
11094#define RCC_APB2ENR_TIM1EN_Pos (11U)
11095#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
11096#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
11097#define RCC_APB2ENR_SPI1EN_Pos (12U)
11098#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
11099#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
11100#define RCC_APB2ENR_TIM8EN_Pos (13U)
11101#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
11102#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
11103#define RCC_APB2ENR_USART1EN_Pos (14U)
11104#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
11105#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
11106#define RCC_APB2ENR_TIM15EN_Pos (16U)
11107#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
11108#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
11109#define RCC_APB2ENR_TIM16EN_Pos (17U)
11110#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
11111#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
11112#define RCC_APB2ENR_TIM17EN_Pos (18U)
11113#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
11114#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
11115#define RCC_APB2ENR_SAI1EN_Pos (21U)
11116#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
11117#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
11118#define RCC_APB2ENR_SAI2EN_Pos (22U)
11119#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
11120#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
11121#define RCC_APB2ENR_DFSDM1EN_Pos (24U)
11122#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
11123#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
11124
11125/******************** Bit definition for RCC_AHB1SMENR register ***************/
11126#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
11127#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)
11128#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
11129#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
11130#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)
11131#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
11132#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
11133#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)
11134#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
11135#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
11136#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)
11137#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
11138#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
11139#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)
11140#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
11141#define RCC_AHB1SMENR_TSCSMEN_Pos (16U)
11142#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos)
11143#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk
11144
11145/******************** Bit definition for RCC_AHB2SMENR register *************/
11146#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
11147#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)
11148#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
11149#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
11150#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)
11151#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
11152#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
11153#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)
11154#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
11155#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
11156#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)
11157#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
11158#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
11159#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)
11160#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
11161#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
11162#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)
11163#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
11164#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
11165#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)
11166#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
11167#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U)
11168#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)
11169#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk
11170#define RCC_AHB2SMENR_SRAM2SMEN_Pos (9U)
11171#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)
11172#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
11173#define RCC_AHB2SMENR_OTGFSSMEN_Pos (12U)
11174#define RCC_AHB2SMENR_OTGFSSMEN_Msk (0x1UL << RCC_AHB2SMENR_OTGFSSMEN_Pos)
11175#define RCC_AHB2SMENR_OTGFSSMEN RCC_AHB2SMENR_OTGFSSMEN_Msk
11176#define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
11177#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos)
11178#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
11179#define RCC_AHB2SMENR_RNGSMEN_Pos (18U)
11180#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)
11181#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
11182
11183/******************** Bit definition for RCC_AHB3SMENR register *************/
11184#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
11185#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)
11186#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
11187#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
11188#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)
11189#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
11190
11191/******************** Bit definition for RCC_APB1SMENR1 register *************/
11192#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
11193#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)
11194#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
11195#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
11196#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)
11197#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
11198#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
11199#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)
11200#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
11201#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
11202#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)
11203#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
11204#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
11205#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)
11206#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
11207#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
11208#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)
11209#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
11210#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
11211#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)
11212#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
11213#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
11214#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)
11215#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
11216#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
11217#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)
11218#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
11219#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
11220#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)
11221#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
11222#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
11223#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)
11224#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
11225#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
11226#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)
11227#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
11228#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
11229#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)
11230#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
11231#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
11232#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)
11233#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
11234#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
11235#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)
11236#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
11237#define RCC_APB1SMENR1_I2C3SMEN_Pos (23U)
11238#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)
11239#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
11240#define RCC_APB1SMENR1_CAN1SMEN_Pos (25U)
11241#define RCC_APB1SMENR1_CAN1SMEN_Msk (0x1UL << RCC_APB1SMENR1_CAN1SMEN_Pos)
11242#define RCC_APB1SMENR1_CAN1SMEN RCC_APB1SMENR1_CAN1SMEN_Msk
11243#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
11244#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)
11245#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
11246#define RCC_APB1SMENR1_DAC1SMEN_Pos (29U)
11247#define RCC_APB1SMENR1_DAC1SMEN_Msk (0x1UL << RCC_APB1SMENR1_DAC1SMEN_Pos)
11248#define RCC_APB1SMENR1_DAC1SMEN RCC_APB1SMENR1_DAC1SMEN_Msk
11249#define RCC_APB1SMENR1_OPAMPSMEN_Pos (30U)
11250#define RCC_APB1SMENR1_OPAMPSMEN_Msk (0x1UL << RCC_APB1SMENR1_OPAMPSMEN_Pos)
11251#define RCC_APB1SMENR1_OPAMPSMEN RCC_APB1SMENR1_OPAMPSMEN_Msk
11252#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
11253#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)
11254#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
11255
11256/******************** Bit definition for RCC_APB1SMENR2 register *************/
11257#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
11258#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)
11259#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
11260#define RCC_APB1SMENR2_SWPMI1SMEN_Pos (2U)
11261#define RCC_APB1SMENR2_SWPMI1SMEN_Msk (0x1UL << RCC_APB1SMENR2_SWPMI1SMEN_Pos)
11262#define RCC_APB1SMENR2_SWPMI1SMEN RCC_APB1SMENR2_SWPMI1SMEN_Msk
11263#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U)
11264#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)
11265#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk
11266
11267/******************** Bit definition for RCC_APB2SMENR register *************/
11268#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
11269#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)
11270#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
11271#define RCC_APB2SMENR_SDMMC1SMEN_Pos (10U)
11272#define RCC_APB2SMENR_SDMMC1SMEN_Msk (0x1UL << RCC_APB2SMENR_SDMMC1SMEN_Pos)
11273#define RCC_APB2SMENR_SDMMC1SMEN RCC_APB2SMENR_SDMMC1SMEN_Msk
11274#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
11275#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)
11276#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
11277#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
11278#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)
11279#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
11280#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
11281#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)
11282#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
11283#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
11284#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)
11285#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
11286#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
11287#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)
11288#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
11289#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
11290#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)
11291#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
11292#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
11293#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)
11294#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
11295#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
11296#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)
11297#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
11298#define RCC_APB2SMENR_SAI2SMEN_Pos (22U)
11299#define RCC_APB2SMENR_SAI2SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos)
11300#define RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk
11301#define RCC_APB2SMENR_DFSDM1SMEN_Pos (24U)
11302#define RCC_APB2SMENR_DFSDM1SMEN_Msk (0x1UL << RCC_APB2SMENR_DFSDM1SMEN_Pos)
11303#define RCC_APB2SMENR_DFSDM1SMEN RCC_APB2SMENR_DFSDM1SMEN_Msk
11304
11305/******************** Bit definition for RCC_CCIPR register ******************/
11306#define RCC_CCIPR_USART1SEL_Pos (0U)
11307#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)
11308#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
11309#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)
11310#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)
11312#define RCC_CCIPR_USART2SEL_Pos (2U)
11313#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)
11314#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
11315#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)
11316#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)
11318#define RCC_CCIPR_USART3SEL_Pos (4U)
11319#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)
11320#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
11321#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)
11322#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)
11324#define RCC_CCIPR_UART4SEL_Pos (6U)
11325#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos)
11326#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
11327#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos)
11328#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos)
11330#define RCC_CCIPR_UART5SEL_Pos (8U)
11331#define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos)
11332#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
11333#define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos)
11334#define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos)
11336#define RCC_CCIPR_LPUART1SEL_Pos (10U)
11337#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)
11338#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
11339#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)
11340#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)
11342#define RCC_CCIPR_I2C1SEL_Pos (12U)
11343#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)
11344#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
11345#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)
11346#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)
11348#define RCC_CCIPR_I2C2SEL_Pos (14U)
11349#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos)
11350#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
11351#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)
11352#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)
11354#define RCC_CCIPR_I2C3SEL_Pos (16U)
11355#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)
11356#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
11357#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)
11358#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)
11360#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
11361#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)
11362#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
11363#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)
11364#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)
11366#define RCC_CCIPR_LPTIM2SEL_Pos (20U)
11367#define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)
11368#define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
11369#define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)
11370#define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)
11372#define RCC_CCIPR_SAI1SEL_Pos (22U)
11373#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)
11374#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
11375#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)
11376#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)
11378#define RCC_CCIPR_SAI2SEL_Pos (24U)
11379#define RCC_CCIPR_SAI2SEL_Msk (0x3UL << RCC_CCIPR_SAI2SEL_Pos)
11380#define RCC_CCIPR_SAI2SEL RCC_CCIPR_SAI2SEL_Msk
11381#define RCC_CCIPR_SAI2SEL_0 (0x1UL << RCC_CCIPR_SAI2SEL_Pos)
11382#define RCC_CCIPR_SAI2SEL_1 (0x2UL << RCC_CCIPR_SAI2SEL_Pos)
11384#define RCC_CCIPR_CLK48SEL_Pos (26U)
11385#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos)
11386#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
11387#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos)
11388#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos)
11390#define RCC_CCIPR_ADCSEL_Pos (28U)
11391#define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos)
11392#define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
11393#define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos)
11394#define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos)
11396#define RCC_CCIPR_SWPMI1SEL_Pos (30U)
11397#define RCC_CCIPR_SWPMI1SEL_Msk (0x1UL << RCC_CCIPR_SWPMI1SEL_Pos)
11398#define RCC_CCIPR_SWPMI1SEL RCC_CCIPR_SWPMI1SEL_Msk
11399
11400#define RCC_CCIPR_DFSDM1SEL_Pos (31U)
11401#define RCC_CCIPR_DFSDM1SEL_Msk (0x1UL << RCC_CCIPR_DFSDM1SEL_Pos)
11402#define RCC_CCIPR_DFSDM1SEL RCC_CCIPR_DFSDM1SEL_Msk
11403
11404/******************** Bit definition for RCC_BDCR register ******************/
11405#define RCC_BDCR_LSEON_Pos (0U)
11406#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
11407#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
11408#define RCC_BDCR_LSERDY_Pos (1U)
11409#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
11410#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
11411#define RCC_BDCR_LSEBYP_Pos (2U)
11412#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
11413#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
11414
11415#define RCC_BDCR_LSEDRV_Pos (3U)
11416#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
11417#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
11418#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
11419#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
11421#define RCC_BDCR_LSECSSON_Pos (5U)
11422#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
11423#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
11424#define RCC_BDCR_LSECSSD_Pos (6U)
11425#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
11426#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
11427
11428#define RCC_BDCR_RTCSEL_Pos (8U)
11429#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
11430#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
11431#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
11432#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
11434#define RCC_BDCR_RTCEN_Pos (15U)
11435#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
11436#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
11437#define RCC_BDCR_BDRST_Pos (16U)
11438#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
11439#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
11440#define RCC_BDCR_LSCOEN_Pos (24U)
11441#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)
11442#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
11443#define RCC_BDCR_LSCOSEL_Pos (25U)
11444#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)
11445#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
11446
11447/******************** Bit definition for RCC_CSR register *******************/
11448#define RCC_CSR_LSION_Pos (0U)
11449#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
11450#define RCC_CSR_LSION RCC_CSR_LSION_Msk
11451#define RCC_CSR_LSIRDY_Pos (1U)
11452#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
11453#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
11454
11455#define RCC_CSR_MSISRANGE_Pos (8U)
11456#define RCC_CSR_MSISRANGE_Msk (0xFUL << RCC_CSR_MSISRANGE_Pos)
11457#define RCC_CSR_MSISRANGE RCC_CSR_MSISRANGE_Msk
11458#define RCC_CSR_MSISRANGE_1 (0x4UL << RCC_CSR_MSISRANGE_Pos)
11459#define RCC_CSR_MSISRANGE_2 (0x5UL << RCC_CSR_MSISRANGE_Pos)
11460#define RCC_CSR_MSISRANGE_4 (0x6UL << RCC_CSR_MSISRANGE_Pos)
11461#define RCC_CSR_MSISRANGE_8 (0x7UL << RCC_CSR_MSISRANGE_Pos)
11463#define RCC_CSR_RMVF_Pos (23U)
11464#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
11465#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
11466#define RCC_CSR_FWRSTF_Pos (24U)
11467#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos)
11468#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk
11469#define RCC_CSR_OBLRSTF_Pos (25U)
11470#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)
11471#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
11472#define RCC_CSR_PINRSTF_Pos (26U)
11473#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
11474#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
11475#define RCC_CSR_BORRSTF_Pos (27U)
11476#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
11477#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
11478#define RCC_CSR_SFTRSTF_Pos (28U)
11479#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
11480#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
11481#define RCC_CSR_IWDGRSTF_Pos (29U)
11482#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
11483#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
11484#define RCC_CSR_WWDGRSTF_Pos (30U)
11485#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
11486#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
11487#define RCC_CSR_LPWRRSTF_Pos (31U)
11488#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
11489#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
11490
11491/******************************************************************************/
11492/* */
11493/* RNG */
11494/* */
11495/******************************************************************************/
11496/******************** Bits definition for RNG_CR register *******************/
11497#define RNG_CR_RNGEN_Pos (2U)
11498#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
11499#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
11500#define RNG_CR_IE_Pos (3U)
11501#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
11502#define RNG_CR_IE RNG_CR_IE_Msk
11503
11504/******************** Bits definition for RNG_SR register *******************/
11505#define RNG_SR_DRDY_Pos (0U)
11506#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
11507#define RNG_SR_DRDY RNG_SR_DRDY_Msk
11508#define RNG_SR_CECS_Pos (1U)
11509#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
11510#define RNG_SR_CECS RNG_SR_CECS_Msk
11511#define RNG_SR_SECS_Pos (2U)
11512#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
11513#define RNG_SR_SECS RNG_SR_SECS_Msk
11514#define RNG_SR_CEIS_Pos (5U)
11515#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
11516#define RNG_SR_CEIS RNG_SR_CEIS_Msk
11517#define RNG_SR_SEIS_Pos (6U)
11518#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
11519#define RNG_SR_SEIS RNG_SR_SEIS_Msk
11520
11521/******************************************************************************/
11522/* */
11523/* Real-Time Clock (RTC) */
11524/* */
11525/******************************************************************************/
11526/*
11527* @brief Specific device feature definitions
11528*/
11529#define RTC_TAMPER1_SUPPORT
11530#define RTC_TAMPER2_SUPPORT
11531#define RTC_TAMPER3_SUPPORT
11532
11533#define RTC_WAKEUP_SUPPORT
11534#define RTC_BACKUP_SUPPORT
11535/******************** Number of backup registers ******************************/
11536#define RTC_BKP_NUMBER 32U
11537
11538
11539/******************** Bits definition for RTC_TR register *******************/
11540#define RTC_TR_PM_Pos (22U)
11541#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
11542#define RTC_TR_PM RTC_TR_PM_Msk
11543#define RTC_TR_HT_Pos (20U)
11544#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
11545#define RTC_TR_HT RTC_TR_HT_Msk
11546#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
11547#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
11548#define RTC_TR_HU_Pos (16U)
11549#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
11550#define RTC_TR_HU RTC_TR_HU_Msk
11551#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
11552#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
11553#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
11554#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
11555#define RTC_TR_MNT_Pos (12U)
11556#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
11557#define RTC_TR_MNT RTC_TR_MNT_Msk
11558#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
11559#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
11560#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
11561#define RTC_TR_MNU_Pos (8U)
11562#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
11563#define RTC_TR_MNU RTC_TR_MNU_Msk
11564#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
11565#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
11566#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
11567#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
11568#define RTC_TR_ST_Pos (4U)
11569#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
11570#define RTC_TR_ST RTC_TR_ST_Msk
11571#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
11572#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
11573#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
11574#define RTC_TR_SU_Pos (0U)
11575#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
11576#define RTC_TR_SU RTC_TR_SU_Msk
11577#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
11578#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
11579#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
11580#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
11582/******************** Bits definition for RTC_DR register *******************/
11583#define RTC_DR_YT_Pos (20U)
11584#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
11585#define RTC_DR_YT RTC_DR_YT_Msk
11586#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
11587#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
11588#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
11589#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
11590#define RTC_DR_YU_Pos (16U)
11591#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
11592#define RTC_DR_YU RTC_DR_YU_Msk
11593#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
11594#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
11595#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
11596#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
11597#define RTC_DR_WDU_Pos (13U)
11598#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
11599#define RTC_DR_WDU RTC_DR_WDU_Msk
11600#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
11601#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
11602#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
11603#define RTC_DR_MT_Pos (12U)
11604#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
11605#define RTC_DR_MT RTC_DR_MT_Msk
11606#define RTC_DR_MU_Pos (8U)
11607#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
11608#define RTC_DR_MU RTC_DR_MU_Msk
11609#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
11610#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
11611#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
11612#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
11613#define RTC_DR_DT_Pos (4U)
11614#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
11615#define RTC_DR_DT RTC_DR_DT_Msk
11616#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
11617#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
11618#define RTC_DR_DU_Pos (0U)
11619#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
11620#define RTC_DR_DU RTC_DR_DU_Msk
11621#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
11622#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
11623#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
11624#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
11626/******************** Bits definition for RTC_CR register *******************/
11627#define RTC_CR_ITSE_Pos (24U)
11628#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
11629#define RTC_CR_ITSE RTC_CR_ITSE_Msk
11630#define RTC_CR_COE_Pos (23U)
11631#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
11632#define RTC_CR_COE RTC_CR_COE_Msk
11633#define RTC_CR_OSEL_Pos (21U)
11634#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
11635#define RTC_CR_OSEL RTC_CR_OSEL_Msk
11636#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
11637#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
11638#define RTC_CR_POL_Pos (20U)
11639#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
11640#define RTC_CR_POL RTC_CR_POL_Msk
11641#define RTC_CR_COSEL_Pos (19U)
11642#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
11643#define RTC_CR_COSEL RTC_CR_COSEL_Msk
11644#define RTC_CR_BKP_Pos (18U)
11645#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
11646#define RTC_CR_BKP RTC_CR_BKP_Msk
11647#define RTC_CR_SUB1H_Pos (17U)
11648#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
11649#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
11650#define RTC_CR_ADD1H_Pos (16U)
11651#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
11652#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
11653#define RTC_CR_TSIE_Pos (15U)
11654#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
11655#define RTC_CR_TSIE RTC_CR_TSIE_Msk
11656#define RTC_CR_WUTIE_Pos (14U)
11657#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
11658#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
11659#define RTC_CR_ALRBIE_Pos (13U)
11660#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
11661#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
11662#define RTC_CR_ALRAIE_Pos (12U)
11663#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
11664#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
11665#define RTC_CR_TSE_Pos (11U)
11666#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
11667#define RTC_CR_TSE RTC_CR_TSE_Msk
11668#define RTC_CR_WUTE_Pos (10U)
11669#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
11670#define RTC_CR_WUTE RTC_CR_WUTE_Msk
11671#define RTC_CR_ALRBE_Pos (9U)
11672#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
11673#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
11674#define RTC_CR_ALRAE_Pos (8U)
11675#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
11676#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
11677#define RTC_CR_FMT_Pos (6U)
11678#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
11679#define RTC_CR_FMT RTC_CR_FMT_Msk
11680#define RTC_CR_BYPSHAD_Pos (5U)
11681#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
11682#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
11683#define RTC_CR_REFCKON_Pos (4U)
11684#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
11685#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
11686#define RTC_CR_TSEDGE_Pos (3U)
11687#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
11688#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
11689#define RTC_CR_WUCKSEL_Pos (0U)
11690#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
11691#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
11692#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
11693#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
11694#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
11696/* Legacy defines */
11697#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
11698#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
11699#define RTC_CR_BCK RTC_CR_BKP
11700
11701/******************** Bits definition for RTC_ISR register ******************/
11702#define RTC_ISR_ITSF_Pos (17U)
11703#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
11704#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
11705#define RTC_ISR_RECALPF_Pos (16U)
11706#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
11707#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
11708#define RTC_ISR_TAMP3F_Pos (15U)
11709#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
11710#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
11711#define RTC_ISR_TAMP2F_Pos (14U)
11712#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
11713#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
11714#define RTC_ISR_TAMP1F_Pos (13U)
11715#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
11716#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
11717#define RTC_ISR_TSOVF_Pos (12U)
11718#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
11719#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
11720#define RTC_ISR_TSF_Pos (11U)
11721#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
11722#define RTC_ISR_TSF RTC_ISR_TSF_Msk
11723#define RTC_ISR_WUTF_Pos (10U)
11724#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
11725#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
11726#define RTC_ISR_ALRBF_Pos (9U)
11727#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
11728#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
11729#define RTC_ISR_ALRAF_Pos (8U)
11730#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
11731#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
11732#define RTC_ISR_INIT_Pos (7U)
11733#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
11734#define RTC_ISR_INIT RTC_ISR_INIT_Msk
11735#define RTC_ISR_INITF_Pos (6U)
11736#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
11737#define RTC_ISR_INITF RTC_ISR_INITF_Msk
11738#define RTC_ISR_RSF_Pos (5U)
11739#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
11740#define RTC_ISR_RSF RTC_ISR_RSF_Msk
11741#define RTC_ISR_INITS_Pos (4U)
11742#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
11743#define RTC_ISR_INITS RTC_ISR_INITS_Msk
11744#define RTC_ISR_SHPF_Pos (3U)
11745#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
11746#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
11747#define RTC_ISR_WUTWF_Pos (2U)
11748#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
11749#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
11750#define RTC_ISR_ALRBWF_Pos (1U)
11751#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
11752#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
11753#define RTC_ISR_ALRAWF_Pos (0U)
11754#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
11755#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
11756
11757/******************** Bits definition for RTC_PRER register *****************/
11758#define RTC_PRER_PREDIV_A_Pos (16U)
11759#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
11760#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
11761#define RTC_PRER_PREDIV_S_Pos (0U)
11762#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
11763#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
11764
11765/******************** Bits definition for RTC_WUTR register *****************/
11766#define RTC_WUTR_WUT_Pos (0U)
11767#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
11768#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
11769
11770/******************** Bits definition for RTC_ALRMAR register ***************/
11771#define RTC_ALRMAR_MSK4_Pos (31U)
11772#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
11773#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
11774#define RTC_ALRMAR_WDSEL_Pos (30U)
11775#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
11776#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
11777#define RTC_ALRMAR_DT_Pos (28U)
11778#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
11779#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
11780#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
11781#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
11782#define RTC_ALRMAR_DU_Pos (24U)
11783#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
11784#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
11785#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
11786#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
11787#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
11788#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
11789#define RTC_ALRMAR_MSK3_Pos (23U)
11790#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
11791#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
11792#define RTC_ALRMAR_PM_Pos (22U)
11793#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
11794#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
11795#define RTC_ALRMAR_HT_Pos (20U)
11796#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
11797#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
11798#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
11799#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
11800#define RTC_ALRMAR_HU_Pos (16U)
11801#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
11802#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
11803#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
11804#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
11805#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
11806#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
11807#define RTC_ALRMAR_MSK2_Pos (15U)
11808#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
11809#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
11810#define RTC_ALRMAR_MNT_Pos (12U)
11811#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
11812#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
11813#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
11814#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
11815#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
11816#define RTC_ALRMAR_MNU_Pos (8U)
11817#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
11818#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
11819#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
11820#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
11821#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
11822#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
11823#define RTC_ALRMAR_MSK1_Pos (7U)
11824#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
11825#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
11826#define RTC_ALRMAR_ST_Pos (4U)
11827#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
11828#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
11829#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
11830#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
11831#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
11832#define RTC_ALRMAR_SU_Pos (0U)
11833#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
11834#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
11835#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
11836#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
11837#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
11838#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
11840/******************** Bits definition for RTC_ALRMBR register ***************/
11841#define RTC_ALRMBR_MSK4_Pos (31U)
11842#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
11843#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
11844#define RTC_ALRMBR_WDSEL_Pos (30U)
11845#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
11846#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
11847#define RTC_ALRMBR_DT_Pos (28U)
11848#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
11849#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
11850#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
11851#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
11852#define RTC_ALRMBR_DU_Pos (24U)
11853#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
11854#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
11855#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
11856#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
11857#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
11858#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
11859#define RTC_ALRMBR_MSK3_Pos (23U)
11860#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
11861#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
11862#define RTC_ALRMBR_PM_Pos (22U)
11863#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
11864#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
11865#define RTC_ALRMBR_HT_Pos (20U)
11866#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
11867#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
11868#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
11869#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
11870#define RTC_ALRMBR_HU_Pos (16U)
11871#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
11872#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
11873#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
11874#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
11875#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
11876#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
11877#define RTC_ALRMBR_MSK2_Pos (15U)
11878#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
11879#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
11880#define RTC_ALRMBR_MNT_Pos (12U)
11881#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
11882#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
11883#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
11884#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
11885#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
11886#define RTC_ALRMBR_MNU_Pos (8U)
11887#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
11888#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
11889#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
11890#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
11891#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
11892#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
11893#define RTC_ALRMBR_MSK1_Pos (7U)
11894#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
11895#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
11896#define RTC_ALRMBR_ST_Pos (4U)
11897#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
11898#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
11899#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
11900#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
11901#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
11902#define RTC_ALRMBR_SU_Pos (0U)
11903#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
11904#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
11905#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
11906#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
11907#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
11908#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
11910/******************** Bits definition for RTC_WPR register ******************/
11911#define RTC_WPR_KEY_Pos (0U)
11912#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
11913#define RTC_WPR_KEY RTC_WPR_KEY_Msk
11914
11915/******************** Bits definition for RTC_SSR register ******************/
11916#define RTC_SSR_SS_Pos (0U)
11917#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
11918#define RTC_SSR_SS RTC_SSR_SS_Msk
11919
11920/******************** Bits definition for RTC_SHIFTR register ***************/
11921#define RTC_SHIFTR_SUBFS_Pos (0U)
11922#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
11923#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
11924#define RTC_SHIFTR_ADD1S_Pos (31U)
11925#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
11926#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
11927
11928/******************** Bits definition for RTC_TSTR register *****************/
11929#define RTC_TSTR_PM_Pos (22U)
11930#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
11931#define RTC_TSTR_PM RTC_TSTR_PM_Msk
11932#define RTC_TSTR_HT_Pos (20U)
11933#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
11934#define RTC_TSTR_HT RTC_TSTR_HT_Msk
11935#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
11936#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
11937#define RTC_TSTR_HU_Pos (16U)
11938#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
11939#define RTC_TSTR_HU RTC_TSTR_HU_Msk
11940#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
11941#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
11942#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
11943#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
11944#define RTC_TSTR_MNT_Pos (12U)
11945#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
11946#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
11947#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
11948#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
11949#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
11950#define RTC_TSTR_MNU_Pos (8U)
11951#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
11952#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
11953#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
11954#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
11955#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
11956#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
11957#define RTC_TSTR_ST_Pos (4U)
11958#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
11959#define RTC_TSTR_ST RTC_TSTR_ST_Msk
11960#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
11961#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
11962#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
11963#define RTC_TSTR_SU_Pos (0U)
11964#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
11965#define RTC_TSTR_SU RTC_TSTR_SU_Msk
11966#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
11967#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
11968#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
11969#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
11971/******************** Bits definition for RTC_TSDR register *****************/
11972#define RTC_TSDR_WDU_Pos (13U)
11973#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
11974#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
11975#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
11976#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
11977#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
11978#define RTC_TSDR_MT_Pos (12U)
11979#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
11980#define RTC_TSDR_MT RTC_TSDR_MT_Msk
11981#define RTC_TSDR_MU_Pos (8U)
11982#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
11983#define RTC_TSDR_MU RTC_TSDR_MU_Msk
11984#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
11985#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
11986#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
11987#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
11988#define RTC_TSDR_DT_Pos (4U)
11989#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
11990#define RTC_TSDR_DT RTC_TSDR_DT_Msk
11991#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
11992#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
11993#define RTC_TSDR_DU_Pos (0U)
11994#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
11995#define RTC_TSDR_DU RTC_TSDR_DU_Msk
11996#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
11997#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
11998#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
11999#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
12001/******************** Bits definition for RTC_TSSSR register ****************/
12002#define RTC_TSSSR_SS_Pos (0U)
12003#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
12004#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
12005
12006/******************** Bits definition for RTC_CAL register *****************/
12007#define RTC_CALR_CALP_Pos (15U)
12008#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
12009#define RTC_CALR_CALP RTC_CALR_CALP_Msk
12010#define RTC_CALR_CALW8_Pos (14U)
12011#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
12012#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
12013#define RTC_CALR_CALW16_Pos (13U)
12014#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
12015#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
12016#define RTC_CALR_CALM_Pos (0U)
12017#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
12018#define RTC_CALR_CALM RTC_CALR_CALM_Msk
12019#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
12020#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
12021#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
12022#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
12023#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
12024#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
12025#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
12026#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
12027#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
12029/******************** Bits definition for RTC_TAMPCR register ***************/
12030#define RTC_TAMPCR_TAMP3MF_Pos (24U)
12031#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
12032#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
12033#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
12034#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
12035#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
12036#define RTC_TAMPCR_TAMP3IE_Pos (22U)
12037#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
12038#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
12039#define RTC_TAMPCR_TAMP2MF_Pos (21U)
12040#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
12041#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
12042#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
12043#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
12044#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
12045#define RTC_TAMPCR_TAMP2IE_Pos (19U)
12046#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
12047#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
12048#define RTC_TAMPCR_TAMP1MF_Pos (18U)
12049#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
12050#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
12051#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
12052#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
12053#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
12054#define RTC_TAMPCR_TAMP1IE_Pos (16U)
12055#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
12056#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
12057#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
12058#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
12059#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
12060#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
12061#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
12062#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
12063#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
12064#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
12065#define RTC_TAMPCR_TAMPFLT_Pos (11U)
12066#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
12067#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
12068#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
12069#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
12070#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
12071#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
12072#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
12073#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
12074#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
12075#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
12076#define RTC_TAMPCR_TAMPTS_Pos (7U)
12077#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
12078#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
12079#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
12080#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
12081#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
12082#define RTC_TAMPCR_TAMP3E_Pos (5U)
12083#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
12084#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
12085#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
12086#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
12087#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
12088#define RTC_TAMPCR_TAMP2E_Pos (3U)
12089#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
12090#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
12091#define RTC_TAMPCR_TAMPIE_Pos (2U)
12092#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
12093#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
12094#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
12095#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
12096#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
12097#define RTC_TAMPCR_TAMP1E_Pos (0U)
12098#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
12099#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
12100
12101/******************** Bits definition for RTC_ALRMASSR register *************/
12102#define RTC_ALRMASSR_MASKSS_Pos (24U)
12103#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
12104#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
12105#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
12106#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
12107#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
12108#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
12109#define RTC_ALRMASSR_SS_Pos (0U)
12110#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
12111#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
12112
12113/******************** Bits definition for RTC_ALRMBSSR register *************/
12114#define RTC_ALRMBSSR_MASKSS_Pos (24U)
12115#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
12116#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
12117#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
12118#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
12119#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
12120#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
12121#define RTC_ALRMBSSR_SS_Pos (0U)
12122#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
12123#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
12124
12125/******************** Bits definition for RTC_0R register *******************/
12126#define RTC_OR_OUT_RMP_Pos (1U)
12127#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
12128#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
12129#define RTC_OR_ALARMOUTTYPE_Pos (0U)
12130#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
12131#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
12132
12133
12134/******************** Bits definition for RTC_BKP0R register ****************/
12135#define RTC_BKP0R_Pos (0U)
12136#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
12137#define RTC_BKP0R RTC_BKP0R_Msk
12138
12139/******************** Bits definition for RTC_BKP1R register ****************/
12140#define RTC_BKP1R_Pos (0U)
12141#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
12142#define RTC_BKP1R RTC_BKP1R_Msk
12143
12144/******************** Bits definition for RTC_BKP2R register ****************/
12145#define RTC_BKP2R_Pos (0U)
12146#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
12147#define RTC_BKP2R RTC_BKP2R_Msk
12148
12149/******************** Bits definition for RTC_BKP3R register ****************/
12150#define RTC_BKP3R_Pos (0U)
12151#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
12152#define RTC_BKP3R RTC_BKP3R_Msk
12153
12154/******************** Bits definition for RTC_BKP4R register ****************/
12155#define RTC_BKP4R_Pos (0U)
12156#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
12157#define RTC_BKP4R RTC_BKP4R_Msk
12158
12159/******************** Bits definition for RTC_BKP5R register ****************/
12160#define RTC_BKP5R_Pos (0U)
12161#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
12162#define RTC_BKP5R RTC_BKP5R_Msk
12163
12164/******************** Bits definition for RTC_BKP6R register ****************/
12165#define RTC_BKP6R_Pos (0U)
12166#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
12167#define RTC_BKP6R RTC_BKP6R_Msk
12168
12169/******************** Bits definition for RTC_BKP7R register ****************/
12170#define RTC_BKP7R_Pos (0U)
12171#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
12172#define RTC_BKP7R RTC_BKP7R_Msk
12173
12174/******************** Bits definition for RTC_BKP8R register ****************/
12175#define RTC_BKP8R_Pos (0U)
12176#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
12177#define RTC_BKP8R RTC_BKP8R_Msk
12178
12179/******************** Bits definition for RTC_BKP9R register ****************/
12180#define RTC_BKP9R_Pos (0U)
12181#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
12182#define RTC_BKP9R RTC_BKP9R_Msk
12183
12184/******************** Bits definition for RTC_BKP10R register ***************/
12185#define RTC_BKP10R_Pos (0U)
12186#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
12187#define RTC_BKP10R RTC_BKP10R_Msk
12188
12189/******************** Bits definition for RTC_BKP11R register ***************/
12190#define RTC_BKP11R_Pos (0U)
12191#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
12192#define RTC_BKP11R RTC_BKP11R_Msk
12193
12194/******************** Bits definition for RTC_BKP12R register ***************/
12195#define RTC_BKP12R_Pos (0U)
12196#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
12197#define RTC_BKP12R RTC_BKP12R_Msk
12198
12199/******************** Bits definition for RTC_BKP13R register ***************/
12200#define RTC_BKP13R_Pos (0U)
12201#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
12202#define RTC_BKP13R RTC_BKP13R_Msk
12203
12204/******************** Bits definition for RTC_BKP14R register ***************/
12205#define RTC_BKP14R_Pos (0U)
12206#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
12207#define RTC_BKP14R RTC_BKP14R_Msk
12208
12209/******************** Bits definition for RTC_BKP15R register ***************/
12210#define RTC_BKP15R_Pos (0U)
12211#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
12212#define RTC_BKP15R RTC_BKP15R_Msk
12213
12214/******************** Bits definition for RTC_BKP16R register ***************/
12215#define RTC_BKP16R_Pos (0U)
12216#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
12217#define RTC_BKP16R RTC_BKP16R_Msk
12218
12219/******************** Bits definition for RTC_BKP17R register ***************/
12220#define RTC_BKP17R_Pos (0U)
12221#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
12222#define RTC_BKP17R RTC_BKP17R_Msk
12223
12224/******************** Bits definition for RTC_BKP18R register ***************/
12225#define RTC_BKP18R_Pos (0U)
12226#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
12227#define RTC_BKP18R RTC_BKP18R_Msk
12228
12229/******************** Bits definition for RTC_BKP19R register ***************/
12230#define RTC_BKP19R_Pos (0U)
12231#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
12232#define RTC_BKP19R RTC_BKP19R_Msk
12233
12234/******************** Bits definition for RTC_BKP20R register ***************/
12235#define RTC_BKP20R_Pos (0U)
12236#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
12237#define RTC_BKP20R RTC_BKP20R_Msk
12238
12239/******************** Bits definition for RTC_BKP21R register ***************/
12240#define RTC_BKP21R_Pos (0U)
12241#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
12242#define RTC_BKP21R RTC_BKP21R_Msk
12243
12244/******************** Bits definition for RTC_BKP22R register ***************/
12245#define RTC_BKP22R_Pos (0U)
12246#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
12247#define RTC_BKP22R RTC_BKP22R_Msk
12248
12249/******************** Bits definition for RTC_BKP23R register ***************/
12250#define RTC_BKP23R_Pos (0U)
12251#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
12252#define RTC_BKP23R RTC_BKP23R_Msk
12253
12254/******************** Bits definition for RTC_BKP24R register ***************/
12255#define RTC_BKP24R_Pos (0U)
12256#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
12257#define RTC_BKP24R RTC_BKP24R_Msk
12258
12259/******************** Bits definition for RTC_BKP25R register ***************/
12260#define RTC_BKP25R_Pos (0U)
12261#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
12262#define RTC_BKP25R RTC_BKP25R_Msk
12263
12264/******************** Bits definition for RTC_BKP26R register ***************/
12265#define RTC_BKP26R_Pos (0U)
12266#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
12267#define RTC_BKP26R RTC_BKP26R_Msk
12268
12269/******************** Bits definition for RTC_BKP27R register ***************/
12270#define RTC_BKP27R_Pos (0U)
12271#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
12272#define RTC_BKP27R RTC_BKP27R_Msk
12273
12274/******************** Bits definition for RTC_BKP28R register ***************/
12275#define RTC_BKP28R_Pos (0U)
12276#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
12277#define RTC_BKP28R RTC_BKP28R_Msk
12278
12279/******************** Bits definition for RTC_BKP29R register ***************/
12280#define RTC_BKP29R_Pos (0U)
12281#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
12282#define RTC_BKP29R RTC_BKP29R_Msk
12283
12284/******************** Bits definition for RTC_BKP30R register ***************/
12285#define RTC_BKP30R_Pos (0U)
12286#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
12287#define RTC_BKP30R RTC_BKP30R_Msk
12288
12289/******************** Bits definition for RTC_BKP31R register ***************/
12290#define RTC_BKP31R_Pos (0U)
12291#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
12292#define RTC_BKP31R RTC_BKP31R_Msk
12293
12294/******************************************************************************/
12295/* */
12296/* Serial Audio Interface */
12297/* */
12298/******************************************************************************/
12299/******************** Bit definition for SAI_GCR register *******************/
12300#define SAI_GCR_SYNCIN_Pos (0U)
12301#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
12302#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
12303#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
12304#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
12306#define SAI_GCR_SYNCOUT_Pos (4U)
12307#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
12308#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
12309#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
12310#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
12312/******************* Bit definition for SAI_xCR1 register *******************/
12313#define SAI_xCR1_MODE_Pos (0U)
12314#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
12315#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
12316#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
12317#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
12319#define SAI_xCR1_PRTCFG_Pos (2U)
12320#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
12321#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
12322#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
12323#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
12325#define SAI_xCR1_DS_Pos (5U)
12326#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
12327#define SAI_xCR1_DS SAI_xCR1_DS_Msk
12328#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
12329#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
12330#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
12332#define SAI_xCR1_LSBFIRST_Pos (8U)
12333#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
12334#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
12335#define SAI_xCR1_CKSTR_Pos (9U)
12336#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
12337#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
12339#define SAI_xCR1_SYNCEN_Pos (10U)
12340#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
12341#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
12342#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
12343#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
12345#define SAI_xCR1_MONO_Pos (12U)
12346#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
12347#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
12348#define SAI_xCR1_OUTDRIV_Pos (13U)
12349#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
12350#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
12351#define SAI_xCR1_SAIEN_Pos (16U)
12352#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
12353#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
12354#define SAI_xCR1_DMAEN_Pos (17U)
12355#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
12356#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
12357#define SAI_xCR1_NODIV_Pos (19U)
12358#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
12359#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
12361#define SAI_xCR1_MCKDIV_Pos (20U)
12362#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
12363#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
12364#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
12365#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
12366#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
12367#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
12369/******************* Bit definition for SAI_xCR2 register *******************/
12370#define SAI_xCR2_FTH_Pos (0U)
12371#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
12372#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
12373#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
12374#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
12375#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
12377#define SAI_xCR2_FFLUSH_Pos (3U)
12378#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
12379#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
12380#define SAI_xCR2_TRIS_Pos (4U)
12381#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
12382#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
12383#define SAI_xCR2_MUTE_Pos (5U)
12384#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
12385#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
12386#define SAI_xCR2_MUTEVAL_Pos (6U)
12387#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
12388#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
12391#define SAI_xCR2_MUTECNT_Pos (7U)
12392#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
12393#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
12394#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
12395#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
12396#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
12397#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
12398#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
12399#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
12401#define SAI_xCR2_CPL_Pos (13U)
12402#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
12403#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
12404#define SAI_xCR2_COMP_Pos (14U)
12405#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
12406#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
12407#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
12408#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
12411/****************** Bit definition for SAI_xFRCR register *******************/
12412#define SAI_xFRCR_FRL_Pos (0U)
12413#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
12414#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
12415#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
12416#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
12417#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
12418#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
12419#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
12420#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
12421#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
12422#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
12424#define SAI_xFRCR_FSALL_Pos (8U)
12425#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
12426#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
12427#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
12428#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
12429#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
12430#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
12431#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
12432#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
12433#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
12435#define SAI_xFRCR_FSDEF_Pos (16U)
12436#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
12437#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
12438#define SAI_xFRCR_FSPOL_Pos (17U)
12439#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
12440#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
12441#define SAI_xFRCR_FSOFF_Pos (18U)
12442#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
12443#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
12445/****************** Bit definition for SAI_xSLOTR register *******************/
12446#define SAI_xSLOTR_FBOFF_Pos (0U)
12447#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
12448#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
12449#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
12450#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
12451#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
12452#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
12453#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
12455#define SAI_xSLOTR_SLOTSZ_Pos (6U)
12456#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
12457#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
12458#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
12459#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
12461#define SAI_xSLOTR_NBSLOT_Pos (8U)
12462#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
12463#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
12464#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
12465#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
12466#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
12467#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
12469#define SAI_xSLOTR_SLOTEN_Pos (16U)
12470#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
12471#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
12473/******************* Bit definition for SAI_xIMR register *******************/
12474#define SAI_xIMR_OVRUDRIE_Pos (0U)
12475#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
12476#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
12477#define SAI_xIMR_MUTEDETIE_Pos (1U)
12478#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
12479#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
12480#define SAI_xIMR_WCKCFGIE_Pos (2U)
12481#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
12482#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
12483#define SAI_xIMR_FREQIE_Pos (3U)
12484#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
12485#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
12486#define SAI_xIMR_CNRDYIE_Pos (4U)
12487#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
12488#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
12489#define SAI_xIMR_AFSDETIE_Pos (5U)
12490#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
12491#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
12492#define SAI_xIMR_LFSDETIE_Pos (6U)
12493#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
12494#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
12496/******************** Bit definition for SAI_xSR register *******************/
12497#define SAI_xSR_OVRUDR_Pos (0U)
12498#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
12499#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
12500#define SAI_xSR_MUTEDET_Pos (1U)
12501#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
12502#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
12503#define SAI_xSR_WCKCFG_Pos (2U)
12504#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
12505#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
12506#define SAI_xSR_FREQ_Pos (3U)
12507#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
12508#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
12509#define SAI_xSR_CNRDY_Pos (4U)
12510#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
12511#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
12512#define SAI_xSR_AFSDET_Pos (5U)
12513#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
12514#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
12515#define SAI_xSR_LFSDET_Pos (6U)
12516#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
12517#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
12519#define SAI_xSR_FLVL_Pos (16U)
12520#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
12521#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
12522#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
12523#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
12524#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
12526/****************** Bit definition for SAI_xCLRFR register ******************/
12527#define SAI_xCLRFR_COVRUDR_Pos (0U)
12528#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
12529#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
12530#define SAI_xCLRFR_CMUTEDET_Pos (1U)
12531#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
12532#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
12533#define SAI_xCLRFR_CWCKCFG_Pos (2U)
12534#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
12535#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
12536#define SAI_xCLRFR_CFREQ_Pos (3U)
12537#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
12538#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
12539#define SAI_xCLRFR_CCNRDY_Pos (4U)
12540#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
12541#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
12542#define SAI_xCLRFR_CAFSDET_Pos (5U)
12543#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
12544#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
12545#define SAI_xCLRFR_CLFSDET_Pos (6U)
12546#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
12547#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
12549/****************** Bit definition for SAI_xDR register ******************/
12550#define SAI_xDR_DATA_Pos (0U)
12551#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
12552#define SAI_xDR_DATA SAI_xDR_DATA_Msk
12553
12554/******************************************************************************/
12555/* */
12556/* SDMMC Interface */
12557/* */
12558/******************************************************************************/
12559/****************** Bit definition for SDMMC_POWER register ******************/
12560#define SDMMC_POWER_PWRCTRL_Pos (0U)
12561#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
12562#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
12563#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
12564#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
12566/****************** Bit definition for SDMMC_CLKCR register ******************/
12567#define SDMMC_CLKCR_CLKDIV_Pos (0U)
12568#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)
12569#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
12570#define SDMMC_CLKCR_CLKEN_Pos (8U)
12571#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos)
12572#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk
12573#define SDMMC_CLKCR_PWRSAV_Pos (9U)
12574#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
12575#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
12576#define SDMMC_CLKCR_BYPASS_Pos (10U)
12577#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos)
12578#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk
12580#define SDMMC_CLKCR_WIDBUS_Pos (11U)
12581#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
12582#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
12583#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
12584#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
12586#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
12587#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
12588#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
12589#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
12590#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
12591#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
12593/******************* Bit definition for SDMMC_ARG register *******************/
12594#define SDMMC_ARG_CMDARG_Pos (0U)
12595#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
12596#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
12598/******************* Bit definition for SDMMC_CMD register *******************/
12599#define SDMMC_CMD_CMDINDEX_Pos (0U)
12600#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
12601#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
12603#define SDMMC_CMD_WAITRESP_Pos (6U)
12604#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
12605#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
12606#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
12607#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
12609#define SDMMC_CMD_WAITINT_Pos (8U)
12610#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
12611#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
12612#define SDMMC_CMD_WAITPEND_Pos (9U)
12613#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
12614#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
12615#define SDMMC_CMD_CPSMEN_Pos (10U)
12616#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
12617#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
12618#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
12619#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)
12620#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk
12622/***************** Bit definition for SDMMC_RESPCMD register *****************/
12623#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
12624#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
12625#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
12627/****************** Bit definition for SDMMC_RESP1 register ******************/
12628#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
12629#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
12630#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
12632/****************** Bit definition for SDMMC_RESP2 register ******************/
12633#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
12634#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
12635#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
12637/****************** Bit definition for SDMMC_RESP3 register ******************/
12638#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
12639#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
12640#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
12642/****************** Bit definition for SDMMC_RESP4 register ******************/
12643#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
12644#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
12645#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
12647/****************** Bit definition for SDMMC_DTIMER register *****************/
12648#define SDMMC_DTIMER_DATATIME_Pos (0U)
12649#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
12650#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
12652/****************** Bit definition for SDMMC_DLEN register *******************/
12653#define SDMMC_DLEN_DATALENGTH_Pos (0U)
12654#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
12655#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
12657/****************** Bit definition for SDMMC_DCTRL register ******************/
12658#define SDMMC_DCTRL_DTEN_Pos (0U)
12659#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
12660#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
12661#define SDMMC_DCTRL_DTDIR_Pos (1U)
12662#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
12663#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
12664#define SDMMC_DCTRL_DTMODE_Pos (2U)
12665#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
12666#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
12667#define SDMMC_DCTRL_DMAEN_Pos (3U)
12668#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos)
12669#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk
12671#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
12672#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12673#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
12674#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12675#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12676#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12677#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
12679#define SDMMC_DCTRL_RWSTART_Pos (8U)
12680#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
12681#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
12682#define SDMMC_DCTRL_RWSTOP_Pos (9U)
12683#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
12684#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
12685#define SDMMC_DCTRL_RWMOD_Pos (10U)
12686#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
12687#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
12688#define SDMMC_DCTRL_SDIOEN_Pos (11U)
12689#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
12690#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
12692/****************** Bit definition for SDMMC_DCOUNT register *****************/
12693#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
12694#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
12695#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
12697/****************** Bit definition for SDMMC_STA register ********************/
12698#define SDMMC_STA_CCRCFAIL_Pos (0U)
12699#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
12700#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
12701#define SDMMC_STA_DCRCFAIL_Pos (1U)
12702#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
12703#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
12704#define SDMMC_STA_CTIMEOUT_Pos (2U)
12705#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
12706#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
12707#define SDMMC_STA_DTIMEOUT_Pos (3U)
12708#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
12709#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
12710#define SDMMC_STA_TXUNDERR_Pos (4U)
12711#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
12712#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
12713#define SDMMC_STA_RXOVERR_Pos (5U)
12714#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
12715#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
12716#define SDMMC_STA_CMDREND_Pos (6U)
12717#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
12718#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
12719#define SDMMC_STA_CMDSENT_Pos (7U)
12720#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
12721#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
12722#define SDMMC_STA_DATAEND_Pos (8U)
12723#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
12724#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
12725#define SDMMC_STA_DBCKEND_Pos (10U)
12726#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
12727#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
12728#define SDMMC_STA_CMDACT_Pos (11U)
12729#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos)
12730#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk
12731#define SDMMC_STA_TXACT_Pos (12U)
12732#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos)
12733#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk
12734#define SDMMC_STA_RXACT_Pos (13U)
12735#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos)
12736#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk
12737#define SDMMC_STA_TXFIFOHE_Pos (14U)
12738#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
12739#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
12740#define SDMMC_STA_RXFIFOHF_Pos (15U)
12741#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
12742#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
12743#define SDMMC_STA_TXFIFOF_Pos (16U)
12744#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
12745#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
12746#define SDMMC_STA_RXFIFOF_Pos (17U)
12747#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
12748#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
12749#define SDMMC_STA_TXFIFOE_Pos (18U)
12750#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
12751#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
12752#define SDMMC_STA_RXFIFOE_Pos (19U)
12753#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
12754#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
12755#define SDMMC_STA_TXDAVL_Pos (20U)
12756#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos)
12757#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk
12758#define SDMMC_STA_RXDAVL_Pos (21U)
12759#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos)
12760#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk
12761#define SDMMC_STA_SDIOIT_Pos (22U)
12762#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
12763#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
12765/* Legacy Defines */
12766#define SDMMC_STA_STBITERR_Pos (9U)
12767#define SDMMC_STA_STBITERR_Msk (0x1UL << SDMMC_STA_STBITERR_Pos)
12768#define SDMMC_STA_STBITERR SDMMC_STA_STBITERR_Msk
12770/******************* Bit definition for SDMMC_ICR register *******************/
12771#define SDMMC_ICR_CCRCFAILC_Pos (0U)
12772#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
12773#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
12774#define SDMMC_ICR_DCRCFAILC_Pos (1U)
12775#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
12776#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
12777#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
12778#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
12779#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
12780#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
12781#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
12782#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
12783#define SDMMC_ICR_TXUNDERRC_Pos (4U)
12784#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
12785#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
12786#define SDMMC_ICR_RXOVERRC_Pos (5U)
12787#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
12788#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
12789#define SDMMC_ICR_CMDRENDC_Pos (6U)
12790#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
12791#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
12792#define SDMMC_ICR_CMDSENTC_Pos (7U)
12793#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
12794#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
12795#define SDMMC_ICR_DATAENDC_Pos (8U)
12796#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
12797#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
12798#define SDMMC_ICR_STBITERRC_Pos (9U)
12799#define SDMMC_ICR_STBITERRC_Msk (0x1UL << SDMMC_ICR_STBITERRC_Pos)
12800#define SDMMC_ICR_STBITERRC SDMMC_ICR_STBITERRC_Msk
12801#define SDMMC_ICR_DBCKENDC_Pos (10U)
12802#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
12803#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
12804#define SDMMC_ICR_SDIOITC_Pos (22U)
12805#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
12806#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
12808/****************** Bit definition for SDMMC_MASK register *******************/
12809#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
12810#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
12811#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
12812#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
12813#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
12814#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
12815#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
12816#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
12817#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
12818#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
12819#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
12820#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
12821#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
12822#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
12823#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
12824#define SDMMC_MASK_RXOVERRIE_Pos (5U)
12825#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
12826#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
12827#define SDMMC_MASK_CMDRENDIE_Pos (6U)
12828#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
12829#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
12830#define SDMMC_MASK_CMDSENTIE_Pos (7U)
12831#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
12832#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
12833#define SDMMC_MASK_DATAENDIE_Pos (8U)
12834#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
12835#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
12836#define SDMMC_MASK_DBCKENDIE_Pos (10U)
12837#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
12838#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
12839#define SDMMC_MASK_CMDACTIE_Pos (11U)
12840#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos)
12841#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk
12842#define SDMMC_MASK_TXACTIE_Pos (12U)
12843#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos)
12844#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk
12845#define SDMMC_MASK_RXACTIE_Pos (13U)
12846#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos)
12847#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk
12848#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
12849#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
12850#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
12851#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
12852#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
12853#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
12854#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
12855#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)
12856#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk
12857#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
12858#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
12859#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
12860#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
12861#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
12862#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
12863#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
12864#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)
12865#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk
12866#define SDMMC_MASK_TXDAVLIE_Pos (20U)
12867#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)
12868#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk
12869#define SDMMC_MASK_RXDAVLIE_Pos (21U)
12870#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)
12871#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk
12872#define SDMMC_MASK_SDIOITIE_Pos (22U)
12873#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
12874#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
12876/***************** Bit definition for SDMMC_FIFOCNT register *****************/
12877#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
12878#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos)
12879#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk
12881/****************** Bit definition for SDMMC_FIFO register *******************/
12882#define SDMMC_FIFO_FIFODATA_Pos (0U)
12883#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
12884#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
12886/******************************************************************************/
12887/* */
12888/* Serial Peripheral Interface (SPI) */
12889/* */
12890/******************************************************************************/
12891/******************* Bit definition for SPI_CR1 register ********************/
12892#define SPI_CR1_CPHA_Pos (0U)
12893#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
12894#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
12895#define SPI_CR1_CPOL_Pos (1U)
12896#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
12897#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
12898#define SPI_CR1_MSTR_Pos (2U)
12899#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
12900#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
12902#define SPI_CR1_BR_Pos (3U)
12903#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
12904#define SPI_CR1_BR SPI_CR1_BR_Msk
12905#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
12906#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
12907#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
12909#define SPI_CR1_SPE_Pos (6U)
12910#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
12911#define SPI_CR1_SPE SPI_CR1_SPE_Msk
12912#define SPI_CR1_LSBFIRST_Pos (7U)
12913#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
12914#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
12915#define SPI_CR1_SSI_Pos (8U)
12916#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
12917#define SPI_CR1_SSI SPI_CR1_SSI_Msk
12918#define SPI_CR1_SSM_Pos (9U)
12919#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
12920#define SPI_CR1_SSM SPI_CR1_SSM_Msk
12921#define SPI_CR1_RXONLY_Pos (10U)
12922#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
12923#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
12924#define SPI_CR1_CRCL_Pos (11U)
12925#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
12926#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
12927#define SPI_CR1_CRCNEXT_Pos (12U)
12928#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
12929#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
12930#define SPI_CR1_CRCEN_Pos (13U)
12931#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
12932#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
12933#define SPI_CR1_BIDIOE_Pos (14U)
12934#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
12935#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
12936#define SPI_CR1_BIDIMODE_Pos (15U)
12937#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
12938#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
12940/******************* Bit definition for SPI_CR2 register ********************/
12941#define SPI_CR2_RXDMAEN_Pos (0U)
12942#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
12943#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
12944#define SPI_CR2_TXDMAEN_Pos (1U)
12945#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
12946#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
12947#define SPI_CR2_SSOE_Pos (2U)
12948#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
12949#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
12950#define SPI_CR2_NSSP_Pos (3U)
12951#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
12952#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
12953#define SPI_CR2_FRF_Pos (4U)
12954#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
12955#define SPI_CR2_FRF SPI_CR2_FRF_Msk
12956#define SPI_CR2_ERRIE_Pos (5U)
12957#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
12958#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
12959#define SPI_CR2_RXNEIE_Pos (6U)
12960#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
12961#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
12962#define SPI_CR2_TXEIE_Pos (7U)
12963#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
12964#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
12965#define SPI_CR2_DS_Pos (8U)
12966#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
12967#define SPI_CR2_DS SPI_CR2_DS_Msk
12968#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
12969#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
12970#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
12971#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
12972#define SPI_CR2_FRXTH_Pos (12U)
12973#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
12974#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
12975#define SPI_CR2_LDMARX_Pos (13U)
12976#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
12977#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
12978#define SPI_CR2_LDMATX_Pos (14U)
12979#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
12980#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
12982/******************** Bit definition for SPI_SR register ********************/
12983#define SPI_SR_RXNE_Pos (0U)
12984#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
12985#define SPI_SR_RXNE SPI_SR_RXNE_Msk
12986#define SPI_SR_TXE_Pos (1U)
12987#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
12988#define SPI_SR_TXE SPI_SR_TXE_Msk
12989#define SPI_SR_CHSIDE_Pos (2U)
12990#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
12991#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
12992#define SPI_SR_UDR_Pos (3U)
12993#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
12994#define SPI_SR_UDR SPI_SR_UDR_Msk
12995#define SPI_SR_CRCERR_Pos (4U)
12996#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
12997#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
12998#define SPI_SR_MODF_Pos (5U)
12999#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
13000#define SPI_SR_MODF SPI_SR_MODF_Msk
13001#define SPI_SR_OVR_Pos (6U)
13002#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
13003#define SPI_SR_OVR SPI_SR_OVR_Msk
13004#define SPI_SR_BSY_Pos (7U)
13005#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
13006#define SPI_SR_BSY SPI_SR_BSY_Msk
13007#define SPI_SR_FRE_Pos (8U)
13008#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
13009#define SPI_SR_FRE SPI_SR_FRE_Msk
13010#define SPI_SR_FRLVL_Pos (9U)
13011#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
13012#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
13013#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
13014#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
13015#define SPI_SR_FTLVL_Pos (11U)
13016#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
13017#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
13018#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
13019#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
13021/******************** Bit definition for SPI_DR register ********************/
13022#define SPI_DR_DR_Pos (0U)
13023#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
13024#define SPI_DR_DR SPI_DR_DR_Msk
13026/******************* Bit definition for SPI_CRCPR register ******************/
13027#define SPI_CRCPR_CRCPOLY_Pos (0U)
13028#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
13029#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
13031/****************** Bit definition for SPI_RXCRCR register ******************/
13032#define SPI_RXCRCR_RXCRC_Pos (0U)
13033#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
13034#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
13036/****************** Bit definition for SPI_TXCRCR register ******************/
13037#define SPI_TXCRCR_TXCRC_Pos (0U)
13038#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
13039#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
13041/******************************************************************************/
13042/* */
13043/* QUADSPI */
13044/* */
13045/******************************************************************************/
13046/***************** Bit definition for QUADSPI_CR register *******************/
13047#define QUADSPI_CR_EN_Pos (0U)
13048#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
13049#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
13050#define QUADSPI_CR_ABORT_Pos (1U)
13051#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
13052#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
13053#define QUADSPI_CR_DMAEN_Pos (2U)
13054#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
13055#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
13056#define QUADSPI_CR_TCEN_Pos (3U)
13057#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
13058#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
13059#define QUADSPI_CR_SSHIFT_Pos (4U)
13060#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
13061#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
13062#define QUADSPI_CR_FTHRES_Pos (8U)
13063#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos)
13064#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
13065#define QUADSPI_CR_TEIE_Pos (16U)
13066#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
13067#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
13068#define QUADSPI_CR_TCIE_Pos (17U)
13069#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
13070#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
13071#define QUADSPI_CR_FTIE_Pos (18U)
13072#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
13073#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
13074#define QUADSPI_CR_SMIE_Pos (19U)
13075#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
13076#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
13077#define QUADSPI_CR_TOIE_Pos (20U)
13078#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
13079#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
13080#define QUADSPI_CR_APMS_Pos (22U)
13081#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
13082#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
13083#define QUADSPI_CR_PMM_Pos (23U)
13084#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
13085#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
13086#define QUADSPI_CR_PRESCALER_Pos (24U)
13087#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
13088#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
13090/***************** Bit definition for QUADSPI_DCR register ******************/
13091#define QUADSPI_DCR_CKMODE_Pos (0U)
13092#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
13093#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
13094#define QUADSPI_DCR_CSHT_Pos (8U)
13095#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
13096#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
13097#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
13098#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
13099#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
13100#define QUADSPI_DCR_FSIZE_Pos (16U)
13101#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
13102#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
13104/****************** Bit definition for QUADSPI_SR register *******************/
13105#define QUADSPI_SR_TEF_Pos (0U)
13106#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
13107#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
13108#define QUADSPI_SR_TCF_Pos (1U)
13109#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
13110#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
13111#define QUADSPI_SR_FTF_Pos (2U)
13112#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
13113#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
13114#define QUADSPI_SR_SMF_Pos (3U)
13115#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
13116#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
13117#define QUADSPI_SR_TOF_Pos (4U)
13118#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
13119#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
13120#define QUADSPI_SR_BUSY_Pos (5U)
13121#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
13122#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
13123#define QUADSPI_SR_FLEVEL_Pos (8U)
13124#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos)
13125#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
13127/****************** Bit definition for QUADSPI_FCR register ******************/
13128#define QUADSPI_FCR_CTEF_Pos (0U)
13129#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
13130#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
13131#define QUADSPI_FCR_CTCF_Pos (1U)
13132#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
13133#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
13134#define QUADSPI_FCR_CSMF_Pos (3U)
13135#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
13136#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
13137#define QUADSPI_FCR_CTOF_Pos (4U)
13138#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
13139#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
13141/****************** Bit definition for QUADSPI_DLR register ******************/
13142#define QUADSPI_DLR_DL_Pos (0U)
13143#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
13144#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
13146/****************** Bit definition for QUADSPI_CCR register ******************/
13147#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13148#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
13149#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
13150#define QUADSPI_CCR_IMODE_Pos (8U)
13151#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
13152#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
13153#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
13154#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
13155#define QUADSPI_CCR_ADMODE_Pos (10U)
13156#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
13157#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
13158#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
13159#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
13160#define QUADSPI_CCR_ADSIZE_Pos (12U)
13161#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
13162#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
13163#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
13164#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
13165#define QUADSPI_CCR_ABMODE_Pos (14U)
13166#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
13167#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
13168#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
13169#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
13170#define QUADSPI_CCR_ABSIZE_Pos (16U)
13171#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
13172#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
13173#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
13174#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
13175#define QUADSPI_CCR_DCYC_Pos (18U)
13176#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
13177#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
13178#define QUADSPI_CCR_DMODE_Pos (24U)
13179#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
13180#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
13181#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
13182#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
13183#define QUADSPI_CCR_FMODE_Pos (26U)
13184#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
13185#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
13186#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
13187#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
13188#define QUADSPI_CCR_SIOO_Pos (28U)
13189#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
13190#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
13191#define QUADSPI_CCR_DDRM_Pos (31U)
13192#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
13193#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
13195/****************** Bit definition for QUADSPI_AR register *******************/
13196#define QUADSPI_AR_ADDRESS_Pos (0U)
13197#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
13198#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
13200/****************** Bit definition for QUADSPI_ABR register ******************/
13201#define QUADSPI_ABR_ALTERNATE_Pos (0U)
13202#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
13203#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
13205/****************** Bit definition for QUADSPI_DR register *******************/
13206#define QUADSPI_DR_DATA_Pos (0U)
13207#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
13208#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
13210/****************** Bit definition for QUADSPI_PSMKR register ****************/
13211#define QUADSPI_PSMKR_MASK_Pos (0U)
13212#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
13213#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
13215/****************** Bit definition for QUADSPI_PSMAR register ****************/
13216#define QUADSPI_PSMAR_MATCH_Pos (0U)
13217#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
13218#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
13220/****************** Bit definition for QUADSPI_PIR register *****************/
13221#define QUADSPI_PIR_INTERVAL_Pos (0U)
13222#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
13223#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
13225/****************** Bit definition for QUADSPI_LPTR register *****************/
13226#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13227#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
13228#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
13230/******************************************************************************/
13231/* */
13232/* SYSCFG */
13233/* */
13234/******************************************************************************/
13235/****************** Bit definition for SYSCFG_MEMRMP register ***************/
13236#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
13237#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13238#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
13239#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13240#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13241#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
13243#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
13244#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)
13245#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk
13247/****************** Bit definition for SYSCFG_CFGR1 register ******************/
13248#define SYSCFG_CFGR1_FWDIS_Pos (0U)
13249#define SYSCFG_CFGR1_FWDIS_Msk (0x1UL << SYSCFG_CFGR1_FWDIS_Pos)
13250#define SYSCFG_CFGR1_FWDIS SYSCFG_CFGR1_FWDIS_Msk
13251#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
13252#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)
13253#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk
13254#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
13255#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)
13256#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk
13257#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
13258#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)
13259#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk
13260#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
13261#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)
13262#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk
13263#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
13264#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)
13265#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk
13266#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
13267#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)
13268#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk
13269#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
13270#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)
13271#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk
13272#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
13273#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)
13274#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk
13275#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000UL)
13276#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000UL)
13277#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000UL)
13278#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000UL)
13279#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000UL)
13280#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000UL)
13282/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
13283#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
13284#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)
13285#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
13286#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
13287#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)
13288#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
13289#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
13290#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)
13291#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
13292#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
13293#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)
13294#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
13299#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000UL)
13300#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001UL)
13301#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002UL)
13302#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003UL)
13303#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004UL)
13304#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005UL)
13305#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006UL)
13306#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007UL)
13311#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000UL)
13312#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010UL)
13313#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020UL)
13314#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030UL)
13315#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040UL)
13316#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050UL)
13317#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060UL)
13318#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070UL)
13323#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000UL)
13324#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100UL)
13325#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200UL)
13326#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300UL)
13327#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400UL)
13328#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500UL)
13329#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600UL)
13334#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000UL)
13335#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000UL)
13336#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000UL)
13337#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000UL)
13338#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000UL)
13339#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000UL)
13340#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000UL)
13342/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
13343#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
13344#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)
13345#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
13346#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
13347#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)
13348#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
13349#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
13350#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)
13351#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
13352#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
13353#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)
13354#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
13358#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000UL)
13359#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001UL)
13360#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002UL)
13361#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003UL)
13362#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004UL)
13363#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005UL)
13364#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006UL)
13369#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000UL)
13370#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010UL)
13371#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020UL)
13372#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030UL)
13373#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040UL)
13374#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050UL)
13375#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060UL)
13380#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000UL)
13381#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100UL)
13382#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200UL)
13383#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300UL)
13384#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400UL)
13385#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500UL)
13386#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600UL)
13391#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000UL)
13392#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000UL)
13393#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000UL)
13394#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000UL)
13395#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000UL)
13396#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000UL)
13397#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000UL)
13399/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
13400#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
13401#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)
13402#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
13403#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
13404#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)
13405#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
13406#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
13407#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)
13408#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
13409#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
13410#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)
13411#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
13416#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000UL)
13417#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001UL)
13418#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002UL)
13419#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003UL)
13420#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004UL)
13421#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005UL)
13422#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006UL)
13427#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000UL)
13428#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010UL)
13429#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020UL)
13430#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030UL)
13431#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040UL)
13432#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050UL)
13433#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060UL)
13438#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000UL)
13439#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100UL)
13440#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200UL)
13441#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300UL)
13442#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400UL)
13443#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500UL)
13444#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600UL)
13449#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000UL)
13450#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000UL)
13451#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000UL)
13452#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000UL)
13453#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000UL)
13454#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000UL)
13455#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000UL)
13457/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
13458#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
13459#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)
13460#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
13461#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
13462#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)
13463#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
13464#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
13465#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)
13466#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
13467#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
13468#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)
13469#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
13474#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000UL)
13475#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001UL)
13476#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002UL)
13477#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003UL)
13478#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004UL)
13479#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005UL)
13480#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006UL)
13485#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000UL)
13486#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010UL)
13487#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020UL)
13488#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030UL)
13489#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040UL)
13490#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050UL)
13491#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060UL)
13496#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000UL)
13497#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100UL)
13498#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200UL)
13499#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300UL)
13500#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400UL)
13501#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500UL)
13502#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600UL)
13507#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000UL)
13508#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000UL)
13509#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000UL)
13510#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000UL)
13511#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000UL)
13512#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000UL)
13513#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000UL)
13515/****************** Bit definition for SYSCFG_SCSR register ****************/
13516#define SYSCFG_SCSR_SRAM2ER_Pos (0U)
13517#define SYSCFG_SCSR_SRAM2ER_Msk (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)
13518#define SYSCFG_SCSR_SRAM2ER SYSCFG_SCSR_SRAM2ER_Msk
13519#define SYSCFG_SCSR_SRAM2BSY_Pos (1U)
13520#define SYSCFG_SCSR_SRAM2BSY_Msk (0x1UL << SYSCFG_SCSR_SRAM2BSY_Pos)
13521#define SYSCFG_SCSR_SRAM2BSY SYSCFG_SCSR_SRAM2BSY_Msk
13523/****************** Bit definition for SYSCFG_CFGR2 register ****************/
13524#define SYSCFG_CFGR2_CLL_Pos (0U)
13525#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)
13526#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk
13527#define SYSCFG_CFGR2_SPL_Pos (1U)
13528#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)
13529#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk
13530#define SYSCFG_CFGR2_PVDL_Pos (2U)
13531#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos)
13532#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk
13533#define SYSCFG_CFGR2_ECCL_Pos (3U)
13534#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)
13535#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk
13536#define SYSCFG_CFGR2_SPF_Pos (8U)
13537#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)
13538#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk
13540/****************** Bit definition for SYSCFG_SWPR register ****************/
13541#define SYSCFG_SWPR_PAGE0_Pos (0U)
13542#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos)
13543#define SYSCFG_SWPR_PAGE0 SYSCFG_SWPR_PAGE0_Msk
13544#define SYSCFG_SWPR_PAGE1_Pos (1U)
13545#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos)
13546#define SYSCFG_SWPR_PAGE1 SYSCFG_SWPR_PAGE1_Msk
13547#define SYSCFG_SWPR_PAGE2_Pos (2U)
13548#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos)
13549#define SYSCFG_SWPR_PAGE2 SYSCFG_SWPR_PAGE2_Msk
13550#define SYSCFG_SWPR_PAGE3_Pos (3U)
13551#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos)
13552#define SYSCFG_SWPR_PAGE3 SYSCFG_SWPR_PAGE3_Msk
13553#define SYSCFG_SWPR_PAGE4_Pos (4U)
13554#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos)
13555#define SYSCFG_SWPR_PAGE4 SYSCFG_SWPR_PAGE4_Msk
13556#define SYSCFG_SWPR_PAGE5_Pos (5U)
13557#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos)
13558#define SYSCFG_SWPR_PAGE5 SYSCFG_SWPR_PAGE5_Msk
13559#define SYSCFG_SWPR_PAGE6_Pos (6U)
13560#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos)
13561#define SYSCFG_SWPR_PAGE6 SYSCFG_SWPR_PAGE6_Msk
13562#define SYSCFG_SWPR_PAGE7_Pos (7U)
13563#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos)
13564#define SYSCFG_SWPR_PAGE7 SYSCFG_SWPR_PAGE7_Msk
13565#define SYSCFG_SWPR_PAGE8_Pos (8U)
13566#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos)
13567#define SYSCFG_SWPR_PAGE8 SYSCFG_SWPR_PAGE8_Msk
13568#define SYSCFG_SWPR_PAGE9_Pos (9U)
13569#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos)
13570#define SYSCFG_SWPR_PAGE9 SYSCFG_SWPR_PAGE9_Msk
13571#define SYSCFG_SWPR_PAGE10_Pos (10U)
13572#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos)
13573#define SYSCFG_SWPR_PAGE10 SYSCFG_SWPR_PAGE10_Msk
13574#define SYSCFG_SWPR_PAGE11_Pos (11U)
13575#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos)
13576#define SYSCFG_SWPR_PAGE11 SYSCFG_SWPR_PAGE11_Msk
13577#define SYSCFG_SWPR_PAGE12_Pos (12U)
13578#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos)
13579#define SYSCFG_SWPR_PAGE12 SYSCFG_SWPR_PAGE12_Msk
13580#define SYSCFG_SWPR_PAGE13_Pos (13U)
13581#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos)
13582#define SYSCFG_SWPR_PAGE13 SYSCFG_SWPR_PAGE13_Msk
13583#define SYSCFG_SWPR_PAGE14_Pos (14U)
13584#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos)
13585#define SYSCFG_SWPR_PAGE14 SYSCFG_SWPR_PAGE14_Msk
13586#define SYSCFG_SWPR_PAGE15_Pos (15U)
13587#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos)
13588#define SYSCFG_SWPR_PAGE15 SYSCFG_SWPR_PAGE15_Msk
13589#define SYSCFG_SWPR_PAGE16_Pos (16U)
13590#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos)
13591#define SYSCFG_SWPR_PAGE16 SYSCFG_SWPR_PAGE16_Msk
13592#define SYSCFG_SWPR_PAGE17_Pos (17U)
13593#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos)
13594#define SYSCFG_SWPR_PAGE17 SYSCFG_SWPR_PAGE17_Msk
13595#define SYSCFG_SWPR_PAGE18_Pos (18U)
13596#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos)
13597#define SYSCFG_SWPR_PAGE18 SYSCFG_SWPR_PAGE18_Msk
13598#define SYSCFG_SWPR_PAGE19_Pos (19U)
13599#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos)
13600#define SYSCFG_SWPR_PAGE19 SYSCFG_SWPR_PAGE19_Msk
13601#define SYSCFG_SWPR_PAGE20_Pos (20U)
13602#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos)
13603#define SYSCFG_SWPR_PAGE20 SYSCFG_SWPR_PAGE20_Msk
13604#define SYSCFG_SWPR_PAGE21_Pos (21U)
13605#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos)
13606#define SYSCFG_SWPR_PAGE21 SYSCFG_SWPR_PAGE21_Msk
13607#define SYSCFG_SWPR_PAGE22_Pos (22U)
13608#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos)
13609#define SYSCFG_SWPR_PAGE22 SYSCFG_SWPR_PAGE22_Msk
13610#define SYSCFG_SWPR_PAGE23_Pos (23U)
13611#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos)
13612#define SYSCFG_SWPR_PAGE23 SYSCFG_SWPR_PAGE23_Msk
13613#define SYSCFG_SWPR_PAGE24_Pos (24U)
13614#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos)
13615#define SYSCFG_SWPR_PAGE24 SYSCFG_SWPR_PAGE24_Msk
13616#define SYSCFG_SWPR_PAGE25_Pos (25U)
13617#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos)
13618#define SYSCFG_SWPR_PAGE25 SYSCFG_SWPR_PAGE25_Msk
13619#define SYSCFG_SWPR_PAGE26_Pos (26U)
13620#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos)
13621#define SYSCFG_SWPR_PAGE26 SYSCFG_SWPR_PAGE26_Msk
13622#define SYSCFG_SWPR_PAGE27_Pos (27U)
13623#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos)
13624#define SYSCFG_SWPR_PAGE27 SYSCFG_SWPR_PAGE27_Msk
13625#define SYSCFG_SWPR_PAGE28_Pos (28U)
13626#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos)
13627#define SYSCFG_SWPR_PAGE28 SYSCFG_SWPR_PAGE28_Msk
13628#define SYSCFG_SWPR_PAGE29_Pos (29U)
13629#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos)
13630#define SYSCFG_SWPR_PAGE29 SYSCFG_SWPR_PAGE29_Msk
13631#define SYSCFG_SWPR_PAGE30_Pos (30U)
13632#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos)
13633#define SYSCFG_SWPR_PAGE30 SYSCFG_SWPR_PAGE30_Msk
13634#define SYSCFG_SWPR_PAGE31_Pos (31U)
13635#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos)
13636#define SYSCFG_SWPR_PAGE31 SYSCFG_SWPR_PAGE31_Msk
13638/****************** Bit definition for SYSCFG_SKR register ****************/
13639#define SYSCFG_SKR_KEY_Pos (0U)
13640#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos)
13641#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk
13646/******************************************************************************/
13647/* */
13648/* TIM */
13649/* */
13650/******************************************************************************/
13651/******************* Bit definition for TIM_CR1 register ********************/
13652#define TIM_CR1_CEN_Pos (0U)
13653#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
13654#define TIM_CR1_CEN TIM_CR1_CEN_Msk
13655#define TIM_CR1_UDIS_Pos (1U)
13656#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
13657#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
13658#define TIM_CR1_URS_Pos (2U)
13659#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
13660#define TIM_CR1_URS TIM_CR1_URS_Msk
13661#define TIM_CR1_OPM_Pos (3U)
13662#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
13663#define TIM_CR1_OPM TIM_CR1_OPM_Msk
13664#define TIM_CR1_DIR_Pos (4U)
13665#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
13666#define TIM_CR1_DIR TIM_CR1_DIR_Msk
13668#define TIM_CR1_CMS_Pos (5U)
13669#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
13670#define TIM_CR1_CMS TIM_CR1_CMS_Msk
13671#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
13672#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
13674#define TIM_CR1_ARPE_Pos (7U)
13675#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
13676#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
13678#define TIM_CR1_CKD_Pos (8U)
13679#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
13680#define TIM_CR1_CKD TIM_CR1_CKD_Msk
13681#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
13682#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
13684#define TIM_CR1_UIFREMAP_Pos (11U)
13685#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
13686#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
13688/******************* Bit definition for TIM_CR2 register ********************/
13689#define TIM_CR2_CCPC_Pos (0U)
13690#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
13691#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
13692#define TIM_CR2_CCUS_Pos (2U)
13693#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
13694#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
13695#define TIM_CR2_CCDS_Pos (3U)
13696#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
13697#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
13699#define TIM_CR2_MMS_Pos (4U)
13700#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
13701#define TIM_CR2_MMS TIM_CR2_MMS_Msk
13702#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
13703#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
13704#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
13706#define TIM_CR2_TI1S_Pos (7U)
13707#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
13708#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
13709#define TIM_CR2_OIS1_Pos (8U)
13710#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
13711#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
13712#define TIM_CR2_OIS1N_Pos (9U)
13713#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
13714#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
13715#define TIM_CR2_OIS2_Pos (10U)
13716#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
13717#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
13718#define TIM_CR2_OIS2N_Pos (11U)
13719#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
13720#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
13721#define TIM_CR2_OIS3_Pos (12U)
13722#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
13723#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
13724#define TIM_CR2_OIS3N_Pos (13U)
13725#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
13726#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
13727#define TIM_CR2_OIS4_Pos (14U)
13728#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
13729#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
13730#define TIM_CR2_OIS5_Pos (16U)
13731#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
13732#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
13733#define TIM_CR2_OIS6_Pos (18U)
13734#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
13735#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
13737#define TIM_CR2_MMS2_Pos (20U)
13738#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
13739#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
13740#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
13741#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
13742#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
13743#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
13745/******************* Bit definition for TIM_SMCR register *******************/
13746#define TIM_SMCR_SMS_Pos (0U)
13747#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
13748#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
13749#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
13750#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
13751#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
13752#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
13754#define TIM_SMCR_OCCS_Pos (3U)
13755#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)
13756#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk
13758#define TIM_SMCR_TS_Pos (4U)
13759#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
13760#define TIM_SMCR_TS TIM_SMCR_TS_Msk
13761#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
13762#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
13763#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
13765#define TIM_SMCR_MSM_Pos (7U)
13766#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
13767#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
13769#define TIM_SMCR_ETF_Pos (8U)
13770#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
13771#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
13772#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
13773#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
13774#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
13775#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
13777#define TIM_SMCR_ETPS_Pos (12U)
13778#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
13779#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
13780#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
13781#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
13783#define TIM_SMCR_ECE_Pos (14U)
13784#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
13785#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
13786#define TIM_SMCR_ETP_Pos (15U)
13787#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
13788#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
13790/******************* Bit definition for TIM_DIER register *******************/
13791#define TIM_DIER_UIE_Pos (0U)
13792#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
13793#define TIM_DIER_UIE TIM_DIER_UIE_Msk
13794#define TIM_DIER_CC1IE_Pos (1U)
13795#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
13796#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
13797#define TIM_DIER_CC2IE_Pos (2U)
13798#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
13799#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
13800#define TIM_DIER_CC3IE_Pos (3U)
13801#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
13802#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
13803#define TIM_DIER_CC4IE_Pos (4U)
13804#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
13805#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
13806#define TIM_DIER_COMIE_Pos (5U)
13807#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
13808#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
13809#define TIM_DIER_TIE_Pos (6U)
13810#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
13811#define TIM_DIER_TIE TIM_DIER_TIE_Msk
13812#define TIM_DIER_BIE_Pos (7U)
13813#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
13814#define TIM_DIER_BIE TIM_DIER_BIE_Msk
13815#define TIM_DIER_UDE_Pos (8U)
13816#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
13817#define TIM_DIER_UDE TIM_DIER_UDE_Msk
13818#define TIM_DIER_CC1DE_Pos (9U)
13819#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
13820#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
13821#define TIM_DIER_CC2DE_Pos (10U)
13822#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
13823#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
13824#define TIM_DIER_CC3DE_Pos (11U)
13825#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
13826#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
13827#define TIM_DIER_CC4DE_Pos (12U)
13828#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
13829#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
13830#define TIM_DIER_COMDE_Pos (13U)
13831#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
13832#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
13833#define TIM_DIER_TDE_Pos (14U)
13834#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
13835#define TIM_DIER_TDE TIM_DIER_TDE_Msk
13837/******************** Bit definition for TIM_SR register ********************/
13838#define TIM_SR_UIF_Pos (0U)
13839#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
13840#define TIM_SR_UIF TIM_SR_UIF_Msk
13841#define TIM_SR_CC1IF_Pos (1U)
13842#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
13843#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
13844#define TIM_SR_CC2IF_Pos (2U)
13845#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
13846#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
13847#define TIM_SR_CC3IF_Pos (3U)
13848#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
13849#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
13850#define TIM_SR_CC4IF_Pos (4U)
13851#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
13852#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
13853#define TIM_SR_COMIF_Pos (5U)
13854#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
13855#define TIM_SR_COMIF TIM_SR_COMIF_Msk
13856#define TIM_SR_TIF_Pos (6U)
13857#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
13858#define TIM_SR_TIF TIM_SR_TIF_Msk
13859#define TIM_SR_BIF_Pos (7U)
13860#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
13861#define TIM_SR_BIF TIM_SR_BIF_Msk
13862#define TIM_SR_B2IF_Pos (8U)
13863#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
13864#define TIM_SR_B2IF TIM_SR_B2IF_Msk
13865#define TIM_SR_CC1OF_Pos (9U)
13866#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
13867#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
13868#define TIM_SR_CC2OF_Pos (10U)
13869#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
13870#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
13871#define TIM_SR_CC3OF_Pos (11U)
13872#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
13873#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
13874#define TIM_SR_CC4OF_Pos (12U)
13875#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
13876#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
13877#define TIM_SR_SBIF_Pos (13U)
13878#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
13879#define TIM_SR_SBIF TIM_SR_SBIF_Msk
13880#define TIM_SR_CC5IF_Pos (16U)
13881#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
13882#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
13883#define TIM_SR_CC6IF_Pos (17U)
13884#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
13885#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
13888/******************* Bit definition for TIM_EGR register ********************/
13889#define TIM_EGR_UG_Pos (0U)
13890#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
13891#define TIM_EGR_UG TIM_EGR_UG_Msk
13892#define TIM_EGR_CC1G_Pos (1U)
13893#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
13894#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
13895#define TIM_EGR_CC2G_Pos (2U)
13896#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
13897#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
13898#define TIM_EGR_CC3G_Pos (3U)
13899#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
13900#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
13901#define TIM_EGR_CC4G_Pos (4U)
13902#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
13903#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
13904#define TIM_EGR_COMG_Pos (5U)
13905#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
13906#define TIM_EGR_COMG TIM_EGR_COMG_Msk
13907#define TIM_EGR_TG_Pos (6U)
13908#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
13909#define TIM_EGR_TG TIM_EGR_TG_Msk
13910#define TIM_EGR_BG_Pos (7U)
13911#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
13912#define TIM_EGR_BG TIM_EGR_BG_Msk
13913#define TIM_EGR_B2G_Pos (8U)
13914#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
13915#define TIM_EGR_B2G TIM_EGR_B2G_Msk
13918/****************** Bit definition for TIM_CCMR1 register *******************/
13919#define TIM_CCMR1_CC1S_Pos (0U)
13920#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
13921#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
13922#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
13923#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
13925#define TIM_CCMR1_OC1FE_Pos (2U)
13926#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
13927#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
13928#define TIM_CCMR1_OC1PE_Pos (3U)
13929#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
13930#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
13932#define TIM_CCMR1_OC1M_Pos (4U)
13933#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
13934#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
13935#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
13936#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
13937#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
13938#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
13940#define TIM_CCMR1_OC1CE_Pos (7U)
13941#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
13942#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
13944#define TIM_CCMR1_CC2S_Pos (8U)
13945#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
13946#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
13947#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
13948#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
13950#define TIM_CCMR1_OC2FE_Pos (10U)
13951#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
13952#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
13953#define TIM_CCMR1_OC2PE_Pos (11U)
13954#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
13955#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
13957#define TIM_CCMR1_OC2M_Pos (12U)
13958#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
13959#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
13960#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
13961#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
13962#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
13963#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
13965#define TIM_CCMR1_OC2CE_Pos (15U)
13966#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
13967#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
13969/*----------------------------------------------------------------------------*/
13970#define TIM_CCMR1_IC1PSC_Pos (2U)
13971#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
13972#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
13973#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
13974#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
13976#define TIM_CCMR1_IC1F_Pos (4U)
13977#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
13978#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
13979#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
13980#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
13981#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
13982#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
13984#define TIM_CCMR1_IC2PSC_Pos (10U)
13985#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
13986#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
13987#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
13988#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
13990#define TIM_CCMR1_IC2F_Pos (12U)
13991#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
13992#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
13993#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
13994#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
13995#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
13996#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
13998/****************** Bit definition for TIM_CCMR2 register *******************/
13999#define TIM_CCMR2_CC3S_Pos (0U)
14000#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
14001#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
14002#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
14003#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
14005#define TIM_CCMR2_OC3FE_Pos (2U)
14006#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
14007#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
14008#define TIM_CCMR2_OC3PE_Pos (3U)
14009#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
14010#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
14012#define TIM_CCMR2_OC3M_Pos (4U)
14013#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
14014#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
14015#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
14016#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
14017#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
14018#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
14020#define TIM_CCMR2_OC3CE_Pos (7U)
14021#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
14022#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
14024#define TIM_CCMR2_CC4S_Pos (8U)
14025#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
14026#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
14027#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
14028#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
14030#define TIM_CCMR2_OC4FE_Pos (10U)
14031#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
14032#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
14033#define TIM_CCMR2_OC4PE_Pos (11U)
14034#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
14035#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
14037#define TIM_CCMR2_OC4M_Pos (12U)
14038#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
14039#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
14040#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
14041#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
14042#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
14043#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
14045#define TIM_CCMR2_OC4CE_Pos (15U)
14046#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
14047#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
14049/*----------------------------------------------------------------------------*/
14050#define TIM_CCMR2_IC3PSC_Pos (2U)
14051#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
14052#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
14053#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
14054#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
14056#define TIM_CCMR2_IC3F_Pos (4U)
14057#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
14058#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
14059#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
14060#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
14061#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
14062#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
14064#define TIM_CCMR2_IC4PSC_Pos (10U)
14065#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
14066#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
14067#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
14068#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
14070#define TIM_CCMR2_IC4F_Pos (12U)
14071#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
14072#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
14073#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
14074#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
14075#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
14076#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
14078/****************** Bit definition for TIM_CCMR3 register *******************/
14079#define TIM_CCMR3_OC5FE_Pos (2U)
14080#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
14081#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
14082#define TIM_CCMR3_OC5PE_Pos (3U)
14083#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
14084#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
14086#define TIM_CCMR3_OC5M_Pos (4U)
14087#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
14088#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
14089#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
14090#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
14091#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
14092#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
14094#define TIM_CCMR3_OC5CE_Pos (7U)
14095#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
14096#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
14098#define TIM_CCMR3_OC6FE_Pos (10U)
14099#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
14100#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
14101#define TIM_CCMR3_OC6PE_Pos (11U)
14102#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
14103#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
14105#define TIM_CCMR3_OC6M_Pos (12U)
14106#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
14107#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
14108#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
14109#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
14110#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
14111#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
14113#define TIM_CCMR3_OC6CE_Pos (15U)
14114#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
14115#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
14117/******************* Bit definition for TIM_CCER register *******************/
14118#define TIM_CCER_CC1E_Pos (0U)
14119#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
14120#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
14121#define TIM_CCER_CC1P_Pos (1U)
14122#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
14123#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
14124#define TIM_CCER_CC1NE_Pos (2U)
14125#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
14126#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
14127#define TIM_CCER_CC1NP_Pos (3U)
14128#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
14129#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
14130#define TIM_CCER_CC2E_Pos (4U)
14131#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
14132#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
14133#define TIM_CCER_CC2P_Pos (5U)
14134#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
14135#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
14136#define TIM_CCER_CC2NE_Pos (6U)
14137#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
14138#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
14139#define TIM_CCER_CC2NP_Pos (7U)
14140#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
14141#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
14142#define TIM_CCER_CC3E_Pos (8U)
14143#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
14144#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
14145#define TIM_CCER_CC3P_Pos (9U)
14146#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
14147#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
14148#define TIM_CCER_CC3NE_Pos (10U)
14149#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
14150#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
14151#define TIM_CCER_CC3NP_Pos (11U)
14152#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
14153#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
14154#define TIM_CCER_CC4E_Pos (12U)
14155#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
14156#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
14157#define TIM_CCER_CC4P_Pos (13U)
14158#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
14159#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
14160#define TIM_CCER_CC4NP_Pos (15U)
14161#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
14162#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
14163#define TIM_CCER_CC5E_Pos (16U)
14164#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
14165#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
14166#define TIM_CCER_CC5P_Pos (17U)
14167#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
14168#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
14169#define TIM_CCER_CC6E_Pos (20U)
14170#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
14171#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
14172#define TIM_CCER_CC6P_Pos (21U)
14173#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
14174#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
14176/******************* Bit definition for TIM_CNT register ********************/
14177#define TIM_CNT_CNT_Pos (0U)
14178#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
14179#define TIM_CNT_CNT TIM_CNT_CNT_Msk
14180#define TIM_CNT_UIFCPY_Pos (31U)
14181#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
14182#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
14184/******************* Bit definition for TIM_PSC register ********************/
14185#define TIM_PSC_PSC_Pos (0U)
14186#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
14187#define TIM_PSC_PSC TIM_PSC_PSC_Msk
14189/******************* Bit definition for TIM_ARR register ********************/
14190#define TIM_ARR_ARR_Pos (0U)
14191#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
14192#define TIM_ARR_ARR TIM_ARR_ARR_Msk
14194/******************* Bit definition for TIM_RCR register ********************/
14195#define TIM_RCR_REP_Pos (0U)
14196#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
14197#define TIM_RCR_REP TIM_RCR_REP_Msk
14199/******************* Bit definition for TIM_CCR1 register *******************/
14200#define TIM_CCR1_CCR1_Pos (0U)
14201#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
14202#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
14204/******************* Bit definition for TIM_CCR2 register *******************/
14205#define TIM_CCR2_CCR2_Pos (0U)
14206#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
14207#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
14209/******************* Bit definition for TIM_CCR3 register *******************/
14210#define TIM_CCR3_CCR3_Pos (0U)
14211#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
14212#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
14214/******************* Bit definition for TIM_CCR4 register *******************/
14215#define TIM_CCR4_CCR4_Pos (0U)
14216#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
14217#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
14219/******************* Bit definition for TIM_CCR5 register *******************/
14220#define TIM_CCR5_CCR5_Pos (0U)
14221#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
14222#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
14223#define TIM_CCR5_GC5C1_Pos (29U)
14224#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
14225#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
14226#define TIM_CCR5_GC5C2_Pos (30U)
14227#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
14228#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
14229#define TIM_CCR5_GC5C3_Pos (31U)
14230#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
14231#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
14233/******************* Bit definition for TIM_CCR6 register *******************/
14234#define TIM_CCR6_CCR6_Pos (0U)
14235#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
14236#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
14238/******************* Bit definition for TIM_BDTR register *******************/
14239#define TIM_BDTR_DTG_Pos (0U)
14240#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
14241#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
14242#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
14243#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
14244#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
14245#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
14246#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
14247#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
14248#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
14249#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
14251#define TIM_BDTR_LOCK_Pos (8U)
14252#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
14253#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
14254#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
14255#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
14257#define TIM_BDTR_OSSI_Pos (10U)
14258#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
14259#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
14260#define TIM_BDTR_OSSR_Pos (11U)
14261#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
14262#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
14263#define TIM_BDTR_BKE_Pos (12U)
14264#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
14265#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
14266#define TIM_BDTR_BKP_Pos (13U)
14267#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
14268#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
14269#define TIM_BDTR_AOE_Pos (14U)
14270#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
14271#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
14272#define TIM_BDTR_MOE_Pos (15U)
14273#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
14274#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
14276#define TIM_BDTR_BKF_Pos (16U)
14277#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
14278#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
14279#define TIM_BDTR_BK2F_Pos (20U)
14280#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
14281#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
14283#define TIM_BDTR_BK2E_Pos (24U)
14284#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
14285#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
14286#define TIM_BDTR_BK2P_Pos (25U)
14287#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
14288#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
14290/******************* Bit definition for TIM_DCR register ********************/
14291#define TIM_DCR_DBA_Pos (0U)
14292#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
14293#define TIM_DCR_DBA TIM_DCR_DBA_Msk
14294#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
14295#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
14296#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
14297#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
14298#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
14300#define TIM_DCR_DBL_Pos (8U)
14301#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
14302#define TIM_DCR_DBL TIM_DCR_DBL_Msk
14303#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
14304#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
14305#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
14306#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
14307#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
14309/******************* Bit definition for TIM_DMAR register *******************/
14310#define TIM_DMAR_DMAB_Pos (0U)
14311#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
14312#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
14314/******************* Bit definition for TIM1_OR1 register *******************/
14315#define TIM1_OR1_ETR_ADC1_RMP_Pos (0U)
14316#define TIM1_OR1_ETR_ADC1_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
14317#define TIM1_OR1_ETR_ADC1_RMP TIM1_OR1_ETR_ADC1_RMP_Msk
14318#define TIM1_OR1_ETR_ADC1_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
14319#define TIM1_OR1_ETR_ADC1_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC1_RMP_Pos)
14321#define TIM1_OR1_ETR_ADC3_RMP_Pos (2U)
14322#define TIM1_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
14323#define TIM1_OR1_ETR_ADC3_RMP TIM1_OR1_ETR_ADC3_RMP_Msk
14324#define TIM1_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
14325#define TIM1_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM1_OR1_ETR_ADC3_RMP_Pos)
14327#define TIM1_OR1_TI1_RMP_Pos (4U)
14328#define TIM1_OR1_TI1_RMP_Msk (0x1UL << TIM1_OR1_TI1_RMP_Pos)
14329#define TIM1_OR1_TI1_RMP TIM1_OR1_TI1_RMP_Msk
14331/******************* Bit definition for TIM1_OR2 register *******************/
14332#define TIM1_OR2_BKINE_Pos (0U)
14333#define TIM1_OR2_BKINE_Msk (0x1UL << TIM1_OR2_BKINE_Pos)
14334#define TIM1_OR2_BKINE TIM1_OR2_BKINE_Msk
14335#define TIM1_OR2_BKCMP1E_Pos (1U)
14336#define TIM1_OR2_BKCMP1E_Msk (0x1UL << TIM1_OR2_BKCMP1E_Pos)
14337#define TIM1_OR2_BKCMP1E TIM1_OR2_BKCMP1E_Msk
14338#define TIM1_OR2_BKCMP2E_Pos (2U)
14339#define TIM1_OR2_BKCMP2E_Msk (0x1UL << TIM1_OR2_BKCMP2E_Pos)
14340#define TIM1_OR2_BKCMP2E TIM1_OR2_BKCMP2E_Msk
14341#define TIM1_OR2_BKDF1BK0E_Pos (8U)
14342#define TIM1_OR2_BKDF1BK0E_Msk (0x1UL << TIM1_OR2_BKDF1BK0E_Pos)
14343#define TIM1_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E_Msk
14344#define TIM1_OR2_BKINP_Pos (9U)
14345#define TIM1_OR2_BKINP_Msk (0x1UL << TIM1_OR2_BKINP_Pos)
14346#define TIM1_OR2_BKINP TIM1_OR2_BKINP_Msk
14347#define TIM1_OR2_BKCMP1P_Pos (10U)
14348#define TIM1_OR2_BKCMP1P_Msk (0x1UL << TIM1_OR2_BKCMP1P_Pos)
14349#define TIM1_OR2_BKCMP1P TIM1_OR2_BKCMP1P_Msk
14350#define TIM1_OR2_BKCMP2P_Pos (11U)
14351#define TIM1_OR2_BKCMP2P_Msk (0x1UL << TIM1_OR2_BKCMP2P_Pos)
14352#define TIM1_OR2_BKCMP2P TIM1_OR2_BKCMP2P_Msk
14354#define TIM1_OR2_ETRSEL_Pos (14U)
14355#define TIM1_OR2_ETRSEL_Msk (0x7UL << TIM1_OR2_ETRSEL_Pos)
14356#define TIM1_OR2_ETRSEL TIM1_OR2_ETRSEL_Msk
14357#define TIM1_OR2_ETRSEL_0 (0x1UL << TIM1_OR2_ETRSEL_Pos)
14358#define TIM1_OR2_ETRSEL_1 (0x2UL << TIM1_OR2_ETRSEL_Pos)
14359#define TIM1_OR2_ETRSEL_2 (0x4UL << TIM1_OR2_ETRSEL_Pos)
14361/******************* Bit definition for TIM1_OR3 register *******************/
14362#define TIM1_OR3_BK2INE_Pos (0U)
14363#define TIM1_OR3_BK2INE_Msk (0x1UL << TIM1_OR3_BK2INE_Pos)
14364#define TIM1_OR3_BK2INE TIM1_OR3_BK2INE_Msk
14365#define TIM1_OR3_BK2CMP1E_Pos (1U)
14366#define TIM1_OR3_BK2CMP1E_Msk (0x1UL << TIM1_OR3_BK2CMP1E_Pos)
14367#define TIM1_OR3_BK2CMP1E TIM1_OR3_BK2CMP1E_Msk
14368#define TIM1_OR3_BK2CMP2E_Pos (2U)
14369#define TIM1_OR3_BK2CMP2E_Msk (0x1UL << TIM1_OR3_BK2CMP2E_Pos)
14370#define TIM1_OR3_BK2CMP2E TIM1_OR3_BK2CMP2E_Msk
14371#define TIM1_OR3_BK2DF1BK1E_Pos (8U)
14372#define TIM1_OR3_BK2DF1BK1E_Msk (0x1UL << TIM1_OR3_BK2DF1BK1E_Pos)
14373#define TIM1_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E_Msk
14374#define TIM1_OR3_BK2INP_Pos (9U)
14375#define TIM1_OR3_BK2INP_Msk (0x1UL << TIM1_OR3_BK2INP_Pos)
14376#define TIM1_OR3_BK2INP TIM1_OR3_BK2INP_Msk
14377#define TIM1_OR3_BK2CMP1P_Pos (10U)
14378#define TIM1_OR3_BK2CMP1P_Msk (0x1UL << TIM1_OR3_BK2CMP1P_Pos)
14379#define TIM1_OR3_BK2CMP1P TIM1_OR3_BK2CMP1P_Msk
14380#define TIM1_OR3_BK2CMP2P_Pos (11U)
14381#define TIM1_OR3_BK2CMP2P_Msk (0x1UL << TIM1_OR3_BK2CMP2P_Pos)
14382#define TIM1_OR3_BK2CMP2P TIM1_OR3_BK2CMP2P_Msk
14384/******************* Bit definition for TIM8_OR1 register *******************/
14385#define TIM8_OR1_ETR_ADC2_RMP_Pos (0U)
14386#define TIM8_OR1_ETR_ADC2_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
14387#define TIM8_OR1_ETR_ADC2_RMP TIM8_OR1_ETR_ADC2_RMP_Msk
14388#define TIM8_OR1_ETR_ADC2_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
14389#define TIM8_OR1_ETR_ADC2_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC2_RMP_Pos)
14391#define TIM8_OR1_ETR_ADC3_RMP_Pos (2U)
14392#define TIM8_OR1_ETR_ADC3_RMP_Msk (0x3UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
14393#define TIM8_OR1_ETR_ADC3_RMP TIM8_OR1_ETR_ADC3_RMP_Msk
14394#define TIM8_OR1_ETR_ADC3_RMP_0 (0x1UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
14395#define TIM8_OR1_ETR_ADC3_RMP_1 (0x2UL << TIM8_OR1_ETR_ADC3_RMP_Pos)
14397#define TIM8_OR1_TI1_RMP_Pos (4U)
14398#define TIM8_OR1_TI1_RMP_Msk (0x1UL << TIM8_OR1_TI1_RMP_Pos)
14399#define TIM8_OR1_TI1_RMP TIM8_OR1_TI1_RMP_Msk
14401/******************* Bit definition for TIM8_OR2 register *******************/
14402#define TIM8_OR2_BKINE_Pos (0U)
14403#define TIM8_OR2_BKINE_Msk (0x1UL << TIM8_OR2_BKINE_Pos)
14404#define TIM8_OR2_BKINE TIM8_OR2_BKINE_Msk
14405#define TIM8_OR2_BKCMP1E_Pos (1U)
14406#define TIM8_OR2_BKCMP1E_Msk (0x1UL << TIM8_OR2_BKCMP1E_Pos)
14407#define TIM8_OR2_BKCMP1E TIM8_OR2_BKCMP1E_Msk
14408#define TIM8_OR2_BKCMP2E_Pos (2U)
14409#define TIM8_OR2_BKCMP2E_Msk (0x1UL << TIM8_OR2_BKCMP2E_Pos)
14410#define TIM8_OR2_BKCMP2E TIM8_OR2_BKCMP2E_Msk
14411#define TIM8_OR2_BKDF1BK2E_Pos (8U)
14412#define TIM8_OR2_BKDF1BK2E_Msk (0x1UL << TIM8_OR2_BKDF1BK2E_Pos)
14413#define TIM8_OR2_BKDF1BK2E TIM8_OR2_BKDF1BK2E_Msk
14414#define TIM8_OR2_BKINP_Pos (9U)
14415#define TIM8_OR2_BKINP_Msk (0x1UL << TIM8_OR2_BKINP_Pos)
14416#define TIM8_OR2_BKINP TIM8_OR2_BKINP_Msk
14417#define TIM8_OR2_BKCMP1P_Pos (10U)
14418#define TIM8_OR2_BKCMP1P_Msk (0x1UL << TIM8_OR2_BKCMP1P_Pos)
14419#define TIM8_OR2_BKCMP1P TIM8_OR2_BKCMP1P_Msk
14420#define TIM8_OR2_BKCMP2P_Pos (11U)
14421#define TIM8_OR2_BKCMP2P_Msk (0x1UL << TIM8_OR2_BKCMP2P_Pos)
14422#define TIM8_OR2_BKCMP2P TIM8_OR2_BKCMP2P_Msk
14424#define TIM8_OR2_ETRSEL_Pos (14U)
14425#define TIM8_OR2_ETRSEL_Msk (0x7UL << TIM8_OR2_ETRSEL_Pos)
14426#define TIM8_OR2_ETRSEL TIM8_OR2_ETRSEL_Msk
14427#define TIM8_OR2_ETRSEL_0 (0x1UL << TIM8_OR2_ETRSEL_Pos)
14428#define TIM8_OR2_ETRSEL_1 (0x2UL << TIM8_OR2_ETRSEL_Pos)
14429#define TIM8_OR2_ETRSEL_2 (0x4UL << TIM8_OR2_ETRSEL_Pos)
14431/******************* Bit definition for TIM8_OR3 register *******************/
14432#define TIM8_OR3_BK2INE_Pos (0U)
14433#define TIM8_OR3_BK2INE_Msk (0x1UL << TIM8_OR3_BK2INE_Pos)
14434#define TIM8_OR3_BK2INE TIM8_OR3_BK2INE_Msk
14435#define TIM8_OR3_BK2CMP1E_Pos (1U)
14436#define TIM8_OR3_BK2CMP1E_Msk (0x1UL << TIM8_OR3_BK2CMP1E_Pos)
14437#define TIM8_OR3_BK2CMP1E TIM8_OR3_BK2CMP1E_Msk
14438#define TIM8_OR3_BK2CMP2E_Pos (2U)
14439#define TIM8_OR3_BK2CMP2E_Msk (0x1UL << TIM8_OR3_BK2CMP2E_Pos)
14440#define TIM8_OR3_BK2CMP2E TIM8_OR3_BK2CMP2E_Msk
14441#define TIM8_OR3_BK2DF1BK3E_Pos (8U)
14442#define TIM8_OR3_BK2DF1BK3E_Msk (0x1UL << TIM8_OR3_BK2DF1BK3E_Pos)
14443#define TIM8_OR3_BK2DF1BK3E TIM8_OR3_BK2DF1BK3E_Msk
14444#define TIM8_OR3_BK2INP_Pos (9U)
14445#define TIM8_OR3_BK2INP_Msk (0x1UL << TIM8_OR3_BK2INP_Pos)
14446#define TIM8_OR3_BK2INP TIM8_OR3_BK2INP_Msk
14447#define TIM8_OR3_BK2CMP1P_Pos (10U)
14448#define TIM8_OR3_BK2CMP1P_Msk (0x1UL << TIM8_OR3_BK2CMP1P_Pos)
14449#define TIM8_OR3_BK2CMP1P TIM8_OR3_BK2CMP1P_Msk
14450#define TIM8_OR3_BK2CMP2P_Pos (11U)
14451#define TIM8_OR3_BK2CMP2P_Msk (0x1UL << TIM8_OR3_BK2CMP2P_Pos)
14452#define TIM8_OR3_BK2CMP2P TIM8_OR3_BK2CMP2P_Msk
14454/******************* Bit definition for TIM2_OR1 register *******************/
14455#define TIM2_OR1_ITR1_RMP_Pos (0U)
14456#define TIM2_OR1_ITR1_RMP_Msk (0x1UL << TIM2_OR1_ITR1_RMP_Pos)
14457#define TIM2_OR1_ITR1_RMP TIM2_OR1_ITR1_RMP_Msk
14458#define TIM2_OR1_ETR1_RMP_Pos (1U)
14459#define TIM2_OR1_ETR1_RMP_Msk (0x1UL << TIM2_OR1_ETR1_RMP_Pos)
14460#define TIM2_OR1_ETR1_RMP TIM2_OR1_ETR1_RMP_Msk
14462#define TIM2_OR1_TI4_RMP_Pos (2U)
14463#define TIM2_OR1_TI4_RMP_Msk (0x3UL << TIM2_OR1_TI4_RMP_Pos)
14464#define TIM2_OR1_TI4_RMP TIM2_OR1_TI4_RMP_Msk
14465#define TIM2_OR1_TI4_RMP_0 (0x1UL << TIM2_OR1_TI4_RMP_Pos)
14466#define TIM2_OR1_TI4_RMP_1 (0x2UL << TIM2_OR1_TI4_RMP_Pos)
14468/******************* Bit definition for TIM2_OR2 register *******************/
14469#define TIM2_OR2_ETRSEL_Pos (14U)
14470#define TIM2_OR2_ETRSEL_Msk (0x7UL << TIM2_OR2_ETRSEL_Pos)
14471#define TIM2_OR2_ETRSEL TIM2_OR2_ETRSEL_Msk
14472#define TIM2_OR2_ETRSEL_0 (0x1UL << TIM2_OR2_ETRSEL_Pos)
14473#define TIM2_OR2_ETRSEL_1 (0x2UL << TIM2_OR2_ETRSEL_Pos)
14474#define TIM2_OR2_ETRSEL_2 (0x4UL << TIM2_OR2_ETRSEL_Pos)
14476/******************* Bit definition for TIM3_OR1 register *******************/
14477#define TIM3_OR1_TI1_RMP_Pos (0U)
14478#define TIM3_OR1_TI1_RMP_Msk (0x3UL << TIM3_OR1_TI1_RMP_Pos)
14479#define TIM3_OR1_TI1_RMP TIM3_OR1_TI1_RMP_Msk
14480#define TIM3_OR1_TI1_RMP_0 (0x1UL << TIM3_OR1_TI1_RMP_Pos)
14481#define TIM3_OR1_TI1_RMP_1 (0x2UL << TIM3_OR1_TI1_RMP_Pos)
14483/******************* Bit definition for TIM3_OR2 register *******************/
14484#define TIM3_OR2_ETRSEL_Pos (14U)
14485#define TIM3_OR2_ETRSEL_Msk (0x7UL << TIM3_OR2_ETRSEL_Pos)
14486#define TIM3_OR2_ETRSEL TIM3_OR2_ETRSEL_Msk
14487#define TIM3_OR2_ETRSEL_0 (0x1UL << TIM3_OR2_ETRSEL_Pos)
14488#define TIM3_OR2_ETRSEL_1 (0x2UL << TIM3_OR2_ETRSEL_Pos)
14489#define TIM3_OR2_ETRSEL_2 (0x4UL << TIM3_OR2_ETRSEL_Pos)
14491/******************* Bit definition for TIM15_OR1 register ******************/
14492#define TIM15_OR1_TI1_RMP_Pos (0U)
14493#define TIM15_OR1_TI1_RMP_Msk (0x1UL << TIM15_OR1_TI1_RMP_Pos)
14494#define TIM15_OR1_TI1_RMP TIM15_OR1_TI1_RMP_Msk
14496#define TIM15_OR1_ENCODER_MODE_Pos (1U)
14497#define TIM15_OR1_ENCODER_MODE_Msk (0x3UL << TIM15_OR1_ENCODER_MODE_Pos)
14498#define TIM15_OR1_ENCODER_MODE TIM15_OR1_ENCODER_MODE_Msk
14499#define TIM15_OR1_ENCODER_MODE_0 (0x1UL << TIM15_OR1_ENCODER_MODE_Pos)
14500#define TIM15_OR1_ENCODER_MODE_1 (0x2UL << TIM15_OR1_ENCODER_MODE_Pos)
14502/******************* Bit definition for TIM15_OR2 register ******************/
14503#define TIM15_OR2_BKINE_Pos (0U)
14504#define TIM15_OR2_BKINE_Msk (0x1UL << TIM15_OR2_BKINE_Pos)
14505#define TIM15_OR2_BKINE TIM15_OR2_BKINE_Msk
14506#define TIM15_OR2_BKCMP1E_Pos (1U)
14507#define TIM15_OR2_BKCMP1E_Msk (0x1UL << TIM15_OR2_BKCMP1E_Pos)
14508#define TIM15_OR2_BKCMP1E TIM15_OR2_BKCMP1E_Msk
14509#define TIM15_OR2_BKCMP2E_Pos (2U)
14510#define TIM15_OR2_BKCMP2E_Msk (0x1UL << TIM15_OR2_BKCMP2E_Pos)
14511#define TIM15_OR2_BKCMP2E TIM15_OR2_BKCMP2E_Msk
14512#define TIM15_OR2_BKDF1BK0E_Pos (8U)
14513#define TIM15_OR2_BKDF1BK0E_Msk (0x1UL << TIM15_OR2_BKDF1BK0E_Pos)
14514#define TIM15_OR2_BKDF1BK0E TIM15_OR2_BKDF1BK0E_Msk
14515#define TIM15_OR2_BKINP_Pos (9U)
14516#define TIM15_OR2_BKINP_Msk (0x1UL << TIM15_OR2_BKINP_Pos)
14517#define TIM15_OR2_BKINP TIM15_OR2_BKINP_Msk
14518#define TIM15_OR2_BKCMP1P_Pos (10U)
14519#define TIM15_OR2_BKCMP1P_Msk (0x1UL << TIM15_OR2_BKCMP1P_Pos)
14520#define TIM15_OR2_BKCMP1P TIM15_OR2_BKCMP1P_Msk
14521#define TIM15_OR2_BKCMP2P_Pos (11U)
14522#define TIM15_OR2_BKCMP2P_Msk (0x1UL << TIM15_OR2_BKCMP2P_Pos)
14523#define TIM15_OR2_BKCMP2P TIM15_OR2_BKCMP2P_Msk
14525/******************* Bit definition for TIM16_OR1 register ******************/
14526#define TIM16_OR1_TI1_RMP_Pos (0U)
14527#define TIM16_OR1_TI1_RMP_Msk (0x3UL << TIM16_OR1_TI1_RMP_Pos)
14528#define TIM16_OR1_TI1_RMP TIM16_OR1_TI1_RMP_Msk
14529#define TIM16_OR1_TI1_RMP_0 (0x1UL << TIM16_OR1_TI1_RMP_Pos)
14530#define TIM16_OR1_TI1_RMP_1 (0x2UL << TIM16_OR1_TI1_RMP_Pos)
14532/******************* Bit definition for TIM16_OR2 register ******************/
14533#define TIM16_OR2_BKINE_Pos (0U)
14534#define TIM16_OR2_BKINE_Msk (0x1UL << TIM16_OR2_BKINE_Pos)
14535#define TIM16_OR2_BKINE TIM16_OR2_BKINE_Msk
14536#define TIM16_OR2_BKCMP1E_Pos (1U)
14537#define TIM16_OR2_BKCMP1E_Msk (0x1UL << TIM16_OR2_BKCMP1E_Pos)
14538#define TIM16_OR2_BKCMP1E TIM16_OR2_BKCMP1E_Msk
14539#define TIM16_OR2_BKCMP2E_Pos (2U)
14540#define TIM16_OR2_BKCMP2E_Msk (0x1UL << TIM16_OR2_BKCMP2E_Pos)
14541#define TIM16_OR2_BKCMP2E TIM16_OR2_BKCMP2E_Msk
14542#define TIM16_OR2_BKDF1BK1E_Pos (8U)
14543#define TIM16_OR2_BKDF1BK1E_Msk (0x1UL << TIM16_OR2_BKDF1BK1E_Pos)
14544#define TIM16_OR2_BKDF1BK1E TIM16_OR2_BKDF1BK1E_Msk
14545#define TIM16_OR2_BKINP_Pos (9U)
14546#define TIM16_OR2_BKINP_Msk (0x1UL << TIM16_OR2_BKINP_Pos)
14547#define TIM16_OR2_BKINP TIM16_OR2_BKINP_Msk
14548#define TIM16_OR2_BKCMP1P_Pos (10U)
14549#define TIM16_OR2_BKCMP1P_Msk (0x1UL << TIM16_OR2_BKCMP1P_Pos)
14550#define TIM16_OR2_BKCMP1P TIM16_OR2_BKCMP1P_Msk
14551#define TIM16_OR2_BKCMP2P_Pos (11U)
14552#define TIM16_OR2_BKCMP2P_Msk (0x1UL << TIM16_OR2_BKCMP2P_Pos)
14553#define TIM16_OR2_BKCMP2P TIM16_OR2_BKCMP2P_Msk
14555/******************* Bit definition for TIM17_OR1 register ******************/
14556#define TIM17_OR1_TI1_RMP_Pos (0U)
14557#define TIM17_OR1_TI1_RMP_Msk (0x3UL << TIM17_OR1_TI1_RMP_Pos)
14558#define TIM17_OR1_TI1_RMP TIM17_OR1_TI1_RMP_Msk
14559#define TIM17_OR1_TI1_RMP_0 (0x1UL << TIM17_OR1_TI1_RMP_Pos)
14560#define TIM17_OR1_TI1_RMP_1 (0x2UL << TIM17_OR1_TI1_RMP_Pos)
14562/******************* Bit definition for TIM17_OR2 register ******************/
14563#define TIM17_OR2_BKINE_Pos (0U)
14564#define TIM17_OR2_BKINE_Msk (0x1UL << TIM17_OR2_BKINE_Pos)
14565#define TIM17_OR2_BKINE TIM17_OR2_BKINE_Msk
14566#define TIM17_OR2_BKCMP1E_Pos (1U)
14567#define TIM17_OR2_BKCMP1E_Msk (0x1UL << TIM17_OR2_BKCMP1E_Pos)
14568#define TIM17_OR2_BKCMP1E TIM17_OR2_BKCMP1E_Msk
14569#define TIM17_OR2_BKCMP2E_Pos (2U)
14570#define TIM17_OR2_BKCMP2E_Msk (0x1UL << TIM17_OR2_BKCMP2E_Pos)
14571#define TIM17_OR2_BKCMP2E TIM17_OR2_BKCMP2E_Msk
14572#define TIM17_OR2_BKDF1BK2E_Pos (8U)
14573#define TIM17_OR2_BKDF1BK2E_Msk (0x1UL << TIM17_OR2_BKDF1BK2E_Pos)
14574#define TIM17_OR2_BKDF1BK2E TIM17_OR2_BKDF1BK2E_Msk
14575#define TIM17_OR2_BKINP_Pos (9U)
14576#define TIM17_OR2_BKINP_Msk (0x1UL << TIM17_OR2_BKINP_Pos)
14577#define TIM17_OR2_BKINP TIM17_OR2_BKINP_Msk
14578#define TIM17_OR2_BKCMP1P_Pos (10U)
14579#define TIM17_OR2_BKCMP1P_Msk (0x1UL << TIM17_OR2_BKCMP1P_Pos)
14580#define TIM17_OR2_BKCMP1P TIM17_OR2_BKCMP1P_Msk
14581#define TIM17_OR2_BKCMP2P_Pos (11U)
14582#define TIM17_OR2_BKCMP2P_Msk (0x1UL << TIM17_OR2_BKCMP2P_Pos)
14583#define TIM17_OR2_BKCMP2P TIM17_OR2_BKCMP2P_Msk
14585/******************************************************************************/
14586/* */
14587/* Low Power Timer (LPTIM) */
14588/* */
14589/******************************************************************************/
14590/****************** Bit definition for LPTIM_ISR register *******************/
14591#define LPTIM_ISR_CMPM_Pos (0U)
14592#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
14593#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
14594#define LPTIM_ISR_ARRM_Pos (1U)
14595#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
14596#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
14597#define LPTIM_ISR_EXTTRIG_Pos (2U)
14598#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
14599#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
14600#define LPTIM_ISR_CMPOK_Pos (3U)
14601#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
14602#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
14603#define LPTIM_ISR_ARROK_Pos (4U)
14604#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
14605#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
14606#define LPTIM_ISR_UP_Pos (5U)
14607#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
14608#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
14609#define LPTIM_ISR_DOWN_Pos (6U)
14610#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
14611#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
14613/****************** Bit definition for LPTIM_ICR register *******************/
14614#define LPTIM_ICR_CMPMCF_Pos (0U)
14615#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
14616#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
14617#define LPTIM_ICR_ARRMCF_Pos (1U)
14618#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
14619#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
14620#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
14621#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
14622#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
14623#define LPTIM_ICR_CMPOKCF_Pos (3U)
14624#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
14625#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
14626#define LPTIM_ICR_ARROKCF_Pos (4U)
14627#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
14628#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
14629#define LPTIM_ICR_UPCF_Pos (5U)
14630#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
14631#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
14632#define LPTIM_ICR_DOWNCF_Pos (6U)
14633#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
14634#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
14636/****************** Bit definition for LPTIM_IER register ********************/
14637#define LPTIM_IER_CMPMIE_Pos (0U)
14638#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
14639#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
14640#define LPTIM_IER_ARRMIE_Pos (1U)
14641#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
14642#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
14643#define LPTIM_IER_EXTTRIGIE_Pos (2U)
14644#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
14645#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
14646#define LPTIM_IER_CMPOKIE_Pos (3U)
14647#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
14648#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
14649#define LPTIM_IER_ARROKIE_Pos (4U)
14650#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
14651#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
14652#define LPTIM_IER_UPIE_Pos (5U)
14653#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
14654#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
14655#define LPTIM_IER_DOWNIE_Pos (6U)
14656#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
14657#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
14659/****************** Bit definition for LPTIM_CFGR register *******************/
14660#define LPTIM_CFGR_CKSEL_Pos (0U)
14661#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
14662#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
14664#define LPTIM_CFGR_CKPOL_Pos (1U)
14665#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
14666#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
14667#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
14668#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
14670#define LPTIM_CFGR_CKFLT_Pos (3U)
14671#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
14672#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
14673#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
14674#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
14676#define LPTIM_CFGR_TRGFLT_Pos (6U)
14677#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
14678#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
14679#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
14680#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
14682#define LPTIM_CFGR_PRESC_Pos (9U)
14683#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
14684#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
14685#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
14686#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
14687#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
14689#define LPTIM_CFGR_TRIGSEL_Pos (13U)
14690#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
14691#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
14692#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
14693#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
14694#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
14696#define LPTIM_CFGR_TRIGEN_Pos (17U)
14697#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
14698#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
14699#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
14700#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
14702#define LPTIM_CFGR_TIMOUT_Pos (19U)
14703#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
14704#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
14705#define LPTIM_CFGR_WAVE_Pos (20U)
14706#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
14707#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
14708#define LPTIM_CFGR_WAVPOL_Pos (21U)
14709#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
14710#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
14711#define LPTIM_CFGR_PRELOAD_Pos (22U)
14712#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
14713#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
14714#define LPTIM_CFGR_COUNTMODE_Pos (23U)
14715#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
14716#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
14717#define LPTIM_CFGR_ENC_Pos (24U)
14718#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
14719#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
14721/****************** Bit definition for LPTIM_CR register ********************/
14722#define LPTIM_CR_ENABLE_Pos (0U)
14723#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
14724#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
14725#define LPTIM_CR_SNGSTRT_Pos (1U)
14726#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
14727#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
14728#define LPTIM_CR_CNTSTRT_Pos (2U)
14729#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
14730#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
14732/****************** Bit definition for LPTIM_CMP register *******************/
14733#define LPTIM_CMP_CMP_Pos (0U)
14734#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
14735#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
14737/****************** Bit definition for LPTIM_ARR register *******************/
14738#define LPTIM_ARR_ARR_Pos (0U)
14739#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
14740#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
14742/****************** Bit definition for LPTIM_CNT register *******************/
14743#define LPTIM_CNT_CNT_Pos (0U)
14744#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
14745#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
14747/****************** Bit definition for LPTIM_OR register ********************/
14748#define LPTIM_OR_OR_Pos (0U)
14749#define LPTIM_OR_OR_Msk (0x3UL << LPTIM_OR_OR_Pos)
14750#define LPTIM_OR_OR LPTIM_OR_OR_Msk
14751#define LPTIM_OR_OR_0 (0x1UL << LPTIM_OR_OR_Pos)
14752#define LPTIM_OR_OR_1 (0x2UL << LPTIM_OR_OR_Pos)
14754/******************************************************************************/
14755/* */
14756/* Analog Comparators (COMP) */
14757/* */
14758/******************************************************************************/
14759/********************** Bit definition for COMP_CSR register ****************/
14760#define COMP_CSR_EN_Pos (0U)
14761#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos)
14762#define COMP_CSR_EN COMP_CSR_EN_Msk
14764#define COMP_CSR_PWRMODE_Pos (2U)
14765#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos)
14766#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk
14767#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos)
14768#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos)
14770#define COMP_CSR_INMSEL_Pos (4U)
14771#define COMP_CSR_INMSEL_Msk (0x7UL << COMP_CSR_INMSEL_Pos)
14772#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk
14773#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos)
14774#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos)
14775#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos)
14777#define COMP_CSR_INPSEL_Pos (7U)
14778#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos)
14779#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk
14780#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos)
14782#define COMP_CSR_WINMODE_Pos (9U)
14783#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos)
14784#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk
14786#define COMP_CSR_POLARITY_Pos (15U)
14787#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos)
14788#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk
14790#define COMP_CSR_HYST_Pos (16U)
14791#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos)
14792#define COMP_CSR_HYST COMP_CSR_HYST_Msk
14793#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos)
14794#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos)
14796#define COMP_CSR_BLANKING_Pos (18U)
14797#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos)
14798#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk
14799#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos)
14800#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos)
14801#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos)
14803#define COMP_CSR_BRGEN_Pos (22U)
14804#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos)
14805#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk
14806#define COMP_CSR_SCALEN_Pos (23U)
14807#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos)
14808#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk
14810#define COMP_CSR_VALUE_Pos (30U)
14811#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos)
14812#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk
14814#define COMP_CSR_LOCK_Pos (31U)
14815#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos)
14816#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk
14818/******************************************************************************/
14819/* */
14820/* Operational Amplifier (OPAMP) */
14821/* */
14822/******************************************************************************/
14823/********************* Bit definition for OPAMPx_CSR register ***************/
14824#define OPAMP_CSR_OPAMPxEN_Pos (0U)
14825#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
14826#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
14827#define OPAMP_CSR_OPALPM_Pos (1U)
14828#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos)
14829#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk
14831#define OPAMP_CSR_OPAMODE_Pos (2U)
14832#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos)
14833#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk
14834#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos)
14835#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos)
14837#define OPAMP_CSR_PGGAIN_Pos (4U)
14838#define OPAMP_CSR_PGGAIN_Msk (0x3UL << OPAMP_CSR_PGGAIN_Pos)
14839#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
14840#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
14841#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
14843#define OPAMP_CSR_VMSEL_Pos (8U)
14844#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
14845#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
14846#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
14847#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
14849#define OPAMP_CSR_VPSEL_Pos (10U)
14850#define OPAMP_CSR_VPSEL_Msk (0x1UL << OPAMP_CSR_VPSEL_Pos)
14851#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
14852#define OPAMP_CSR_CALON_Pos (12U)
14853#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
14854#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
14855#define OPAMP_CSR_CALSEL_Pos (13U)
14856#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos)
14857#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
14858#define OPAMP_CSR_USERTRIM_Pos (14U)
14859#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
14860#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
14861#define OPAMP_CSR_CALOUT_Pos (15U)
14862#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
14863#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
14865/********************* Bit definition for OPAMP1_CSR register ***************/
14866#define OPAMP1_CSR_OPAEN_Pos (0U)
14867#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
14868#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
14869#define OPAMP1_CSR_OPALPM_Pos (1U)
14870#define OPAMP1_CSR_OPALPM_Msk (0x1UL << OPAMP1_CSR_OPALPM_Pos)
14871#define OPAMP1_CSR_OPALPM OPAMP1_CSR_OPALPM_Msk
14873#define OPAMP1_CSR_OPAMODE_Pos (2U)
14874#define OPAMP1_CSR_OPAMODE_Msk (0x3UL << OPAMP1_CSR_OPAMODE_Pos)
14875#define OPAMP1_CSR_OPAMODE OPAMP1_CSR_OPAMODE_Msk
14876#define OPAMP1_CSR_OPAMODE_0 (0x1UL << OPAMP1_CSR_OPAMODE_Pos)
14877#define OPAMP1_CSR_OPAMODE_1 (0x2UL << OPAMP1_CSR_OPAMODE_Pos)
14879#define OPAMP1_CSR_PGAGAIN_Pos (4U)
14880#define OPAMP1_CSR_PGAGAIN_Msk (0x3UL << OPAMP1_CSR_PGAGAIN_Pos)
14881#define OPAMP1_CSR_PGAGAIN OPAMP1_CSR_PGAGAIN_Msk
14882#define OPAMP1_CSR_PGAGAIN_0 (0x1UL << OPAMP1_CSR_PGAGAIN_Pos)
14883#define OPAMP1_CSR_PGAGAIN_1 (0x2UL << OPAMP1_CSR_PGAGAIN_Pos)
14885#define OPAMP1_CSR_VMSEL_Pos (8U)
14886#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
14887#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
14888#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
14889#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
14891#define OPAMP1_CSR_VPSEL_Pos (10U)
14892#define OPAMP1_CSR_VPSEL_Msk (0x1UL << OPAMP1_CSR_VPSEL_Pos)
14893#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
14894#define OPAMP1_CSR_CALON_Pos (12U)
14895#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
14896#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
14897#define OPAMP1_CSR_CALSEL_Pos (13U)
14898#define OPAMP1_CSR_CALSEL_Msk (0x1UL << OPAMP1_CSR_CALSEL_Pos)
14899#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
14900#define OPAMP1_CSR_USERTRIM_Pos (14U)
14901#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
14902#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
14903#define OPAMP1_CSR_CALOUT_Pos (15U)
14904#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
14905#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
14907#define OPAMP1_CSR_OPARANGE_Pos (31U)
14908#define OPAMP1_CSR_OPARANGE_Msk (0x1UL << OPAMP1_CSR_OPARANGE_Pos)
14909#define OPAMP1_CSR_OPARANGE OPAMP1_CSR_OPARANGE_Msk
14911/********************* Bit definition for OPAMP2_CSR register ***************/
14912#define OPAMP2_CSR_OPAEN_Pos (0U)
14913#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
14914#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
14915#define OPAMP2_CSR_OPALPM_Pos (1U)
14916#define OPAMP2_CSR_OPALPM_Msk (0x1UL << OPAMP2_CSR_OPALPM_Pos)
14917#define OPAMP2_CSR_OPALPM OPAMP2_CSR_OPALPM_Msk
14919#define OPAMP2_CSR_OPAMODE_Pos (2U)
14920#define OPAMP2_CSR_OPAMODE_Msk (0x3UL << OPAMP2_CSR_OPAMODE_Pos)
14921#define OPAMP2_CSR_OPAMODE OPAMP2_CSR_OPAMODE_Msk
14922#define OPAMP2_CSR_OPAMODE_0 (0x1UL << OPAMP2_CSR_OPAMODE_Pos)
14923#define OPAMP2_CSR_OPAMODE_1 (0x2UL << OPAMP2_CSR_OPAMODE_Pos)
14925#define OPAMP2_CSR_PGAGAIN_Pos (4U)
14926#define OPAMP2_CSR_PGAGAIN_Msk (0x3UL << OPAMP2_CSR_PGAGAIN_Pos)
14927#define OPAMP2_CSR_PGAGAIN OPAMP2_CSR_PGAGAIN_Msk
14928#define OPAMP2_CSR_PGAGAIN_0 (0x1UL << OPAMP2_CSR_PGAGAIN_Pos)
14929#define OPAMP2_CSR_PGAGAIN_1 (0x2UL << OPAMP2_CSR_PGAGAIN_Pos)
14931#define OPAMP2_CSR_VMSEL_Pos (8U)
14932#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
14933#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
14934#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
14935#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
14937#define OPAMP2_CSR_VPSEL_Pos (10U)
14938#define OPAMP2_CSR_VPSEL_Msk (0x1UL << OPAMP2_CSR_VPSEL_Pos)
14939#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
14940#define OPAMP2_CSR_CALON_Pos (12U)
14941#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
14942#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
14943#define OPAMP2_CSR_CALSEL_Pos (13U)
14944#define OPAMP2_CSR_CALSEL_Msk (0x1UL << OPAMP2_CSR_CALSEL_Pos)
14945#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
14946#define OPAMP2_CSR_USERTRIM_Pos (14U)
14947#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
14948#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
14949#define OPAMP2_CSR_CALOUT_Pos (15U)
14950#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
14951#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
14953/******************* Bit definition for OPAMP_OTR register ******************/
14954#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
14955#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
14956#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
14957#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
14958#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
14959#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
14961/******************* Bit definition for OPAMP1_OTR register ******************/
14962#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
14963#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
14964#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
14965#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
14966#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
14967#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
14969/******************* Bit definition for OPAMP2_OTR register ******************/
14970#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
14971#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
14972#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
14973#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
14974#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
14975#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
14977/******************* Bit definition for OPAMP_LPOTR register ****************/
14978#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U)
14979#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos)
14980#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk
14981#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U)
14982#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos)
14983#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk
14985/******************* Bit definition for OPAMP1_LPOTR register ****************/
14986#define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos (0U)
14987#define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos)
14988#define OPAMP1_LPOTR_TRIMLPOFFSETN OPAMP1_LPOTR_TRIMLPOFFSETN_Msk
14989#define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos (8U)
14990#define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos)
14991#define OPAMP1_LPOTR_TRIMLPOFFSETP OPAMP1_LPOTR_TRIMLPOFFSETP_Msk
14993/******************* Bit definition for OPAMP2_LPOTR register ****************/
14994#define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos (0U)
14995#define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos)
14996#define OPAMP2_LPOTR_TRIMLPOFFSETN OPAMP2_LPOTR_TRIMLPOFFSETN_Msk
14997#define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos (8U)
14998#define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos)
14999#define OPAMP2_LPOTR_TRIMLPOFFSETP OPAMP2_LPOTR_TRIMLPOFFSETP_Msk
15001/******************************************************************************/
15002/* */
15003/* Touch Sensing Controller (TSC) */
15004/* */
15005/******************************************************************************/
15006/******************* Bit definition for TSC_CR register *********************/
15007#define TSC_CR_TSCE_Pos (0U)
15008#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos)
15009#define TSC_CR_TSCE TSC_CR_TSCE_Msk
15010#define TSC_CR_START_Pos (1U)
15011#define TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos)
15012#define TSC_CR_START TSC_CR_START_Msk
15013#define TSC_CR_AM_Pos (2U)
15014#define TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos)
15015#define TSC_CR_AM TSC_CR_AM_Msk
15016#define TSC_CR_SYNCPOL_Pos (3U)
15017#define TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos)
15018#define TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk
15019#define TSC_CR_IODEF_Pos (4U)
15020#define TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos)
15021#define TSC_CR_IODEF TSC_CR_IODEF_Msk
15023#define TSC_CR_MCV_Pos (5U)
15024#define TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos)
15025#define TSC_CR_MCV TSC_CR_MCV_Msk
15026#define TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos)
15027#define TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos)
15028#define TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos)
15030#define TSC_CR_PGPSC_Pos (12U)
15031#define TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos)
15032#define TSC_CR_PGPSC TSC_CR_PGPSC_Msk
15033#define TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos)
15034#define TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos)
15035#define TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos)
15037#define TSC_CR_SSPSC_Pos (15U)
15038#define TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos)
15039#define TSC_CR_SSPSC TSC_CR_SSPSC_Msk
15040#define TSC_CR_SSE_Pos (16U)
15041#define TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos)
15042#define TSC_CR_SSE TSC_CR_SSE_Msk
15044#define TSC_CR_SSD_Pos (17U)
15045#define TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos)
15046#define TSC_CR_SSD TSC_CR_SSD_Msk
15047#define TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos)
15048#define TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos)
15049#define TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos)
15050#define TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos)
15051#define TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos)
15052#define TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos)
15053#define TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos)
15055#define TSC_CR_CTPL_Pos (24U)
15056#define TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos)
15057#define TSC_CR_CTPL TSC_CR_CTPL_Msk
15058#define TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos)
15059#define TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos)
15060#define TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos)
15061#define TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos)
15063#define TSC_CR_CTPH_Pos (28U)
15064#define TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos)
15065#define TSC_CR_CTPH TSC_CR_CTPH_Msk
15066#define TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos)
15067#define TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos)
15068#define TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos)
15069#define TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos)
15071/******************* Bit definition for TSC_IER register ********************/
15072#define TSC_IER_EOAIE_Pos (0U)
15073#define TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos)
15074#define TSC_IER_EOAIE TSC_IER_EOAIE_Msk
15075#define TSC_IER_MCEIE_Pos (1U)
15076#define TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos)
15077#define TSC_IER_MCEIE TSC_IER_MCEIE_Msk
15079/******************* Bit definition for TSC_ICR register ********************/
15080#define TSC_ICR_EOAIC_Pos (0U)
15081#define TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos)
15082#define TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk
15083#define TSC_ICR_MCEIC_Pos (1U)
15084#define TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos)
15085#define TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk
15087/******************* Bit definition for TSC_ISR register ********************/
15088#define TSC_ISR_EOAF_Pos (0U)
15089#define TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos)
15090#define TSC_ISR_EOAF TSC_ISR_EOAF_Msk
15091#define TSC_ISR_MCEF_Pos (1U)
15092#define TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos)
15093#define TSC_ISR_MCEF TSC_ISR_MCEF_Msk
15095/******************* Bit definition for TSC_IOHCR register ******************/
15096#define TSC_IOHCR_G1_IO1_Pos (0U)
15097#define TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos)
15098#define TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk
15099#define TSC_IOHCR_G1_IO2_Pos (1U)
15100#define TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos)
15101#define TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk
15102#define TSC_IOHCR_G1_IO3_Pos (2U)
15103#define TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos)
15104#define TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk
15105#define TSC_IOHCR_G1_IO4_Pos (3U)
15106#define TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos)
15107#define TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk
15108#define TSC_IOHCR_G2_IO1_Pos (4U)
15109#define TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos)
15110#define TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk
15111#define TSC_IOHCR_G2_IO2_Pos (5U)
15112#define TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos)
15113#define TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk
15114#define TSC_IOHCR_G2_IO3_Pos (6U)
15115#define TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos)
15116#define TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk
15117#define TSC_IOHCR_G2_IO4_Pos (7U)
15118#define TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos)
15119#define TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk
15120#define TSC_IOHCR_G3_IO1_Pos (8U)
15121#define TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos)
15122#define TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk
15123#define TSC_IOHCR_G3_IO2_Pos (9U)
15124#define TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos)
15125#define TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk
15126#define TSC_IOHCR_G3_IO3_Pos (10U)
15127#define TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos)
15128#define TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk
15129#define TSC_IOHCR_G3_IO4_Pos (11U)
15130#define TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos)
15131#define TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk
15132#define TSC_IOHCR_G4_IO1_Pos (12U)
15133#define TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos)
15134#define TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk
15135#define TSC_IOHCR_G4_IO2_Pos (13U)
15136#define TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos)
15137#define TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk
15138#define TSC_IOHCR_G4_IO3_Pos (14U)
15139#define TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos)
15140#define TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk
15141#define TSC_IOHCR_G4_IO4_Pos (15U)
15142#define TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos)
15143#define TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk
15144#define TSC_IOHCR_G5_IO1_Pos (16U)
15145#define TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos)
15146#define TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk
15147#define TSC_IOHCR_G5_IO2_Pos (17U)
15148#define TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos)
15149#define TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk
15150#define TSC_IOHCR_G5_IO3_Pos (18U)
15151#define TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos)
15152#define TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk
15153#define TSC_IOHCR_G5_IO4_Pos (19U)
15154#define TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos)
15155#define TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk
15156#define TSC_IOHCR_G6_IO1_Pos (20U)
15157#define TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos)
15158#define TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk
15159#define TSC_IOHCR_G6_IO2_Pos (21U)
15160#define TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos)
15161#define TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk
15162#define TSC_IOHCR_G6_IO3_Pos (22U)
15163#define TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos)
15164#define TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk
15165#define TSC_IOHCR_G6_IO4_Pos (23U)
15166#define TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos)
15167#define TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk
15168#define TSC_IOHCR_G7_IO1_Pos (24U)
15169#define TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos)
15170#define TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk
15171#define TSC_IOHCR_G7_IO2_Pos (25U)
15172#define TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos)
15173#define TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk
15174#define TSC_IOHCR_G7_IO3_Pos (26U)
15175#define TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos)
15176#define TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk
15177#define TSC_IOHCR_G7_IO4_Pos (27U)
15178#define TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos)
15179#define TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk
15180#define TSC_IOHCR_G8_IO1_Pos (28U)
15181#define TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos)
15182#define TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk
15183#define TSC_IOHCR_G8_IO2_Pos (29U)
15184#define TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos)
15185#define TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk
15186#define TSC_IOHCR_G8_IO3_Pos (30U)
15187#define TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos)
15188#define TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk
15189#define TSC_IOHCR_G8_IO4_Pos (31U)
15190#define TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos)
15191#define TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk
15193/******************* Bit definition for TSC_IOASCR register *****************/
15194#define TSC_IOASCR_G1_IO1_Pos (0U)
15195#define TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos)
15196#define TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk
15197#define TSC_IOASCR_G1_IO2_Pos (1U)
15198#define TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos)
15199#define TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk
15200#define TSC_IOASCR_G1_IO3_Pos (2U)
15201#define TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos)
15202#define TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk
15203#define TSC_IOASCR_G1_IO4_Pos (3U)
15204#define TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos)
15205#define TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk
15206#define TSC_IOASCR_G2_IO1_Pos (4U)
15207#define TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos)
15208#define TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk
15209#define TSC_IOASCR_G2_IO2_Pos (5U)
15210#define TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos)
15211#define TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk
15212#define TSC_IOASCR_G2_IO3_Pos (6U)
15213#define TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos)
15214#define TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk
15215#define TSC_IOASCR_G2_IO4_Pos (7U)
15216#define TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos)
15217#define TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk
15218#define TSC_IOASCR_G3_IO1_Pos (8U)
15219#define TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos)
15220#define TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk
15221#define TSC_IOASCR_G3_IO2_Pos (9U)
15222#define TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos)
15223#define TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk
15224#define TSC_IOASCR_G3_IO3_Pos (10U)
15225#define TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos)
15226#define TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk
15227#define TSC_IOASCR_G3_IO4_Pos (11U)
15228#define TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos)
15229#define TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk
15230#define TSC_IOASCR_G4_IO1_Pos (12U)
15231#define TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos)
15232#define TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk
15233#define TSC_IOASCR_G4_IO2_Pos (13U)
15234#define TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos)
15235#define TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk
15236#define TSC_IOASCR_G4_IO3_Pos (14U)
15237#define TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos)
15238#define TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk
15239#define TSC_IOASCR_G4_IO4_Pos (15U)
15240#define TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos)
15241#define TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk
15242#define TSC_IOASCR_G5_IO1_Pos (16U)
15243#define TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos)
15244#define TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk
15245#define TSC_IOASCR_G5_IO2_Pos (17U)
15246#define TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos)
15247#define TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk
15248#define TSC_IOASCR_G5_IO3_Pos (18U)
15249#define TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos)
15250#define TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk
15251#define TSC_IOASCR_G5_IO4_Pos (19U)
15252#define TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos)
15253#define TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk
15254#define TSC_IOASCR_G6_IO1_Pos (20U)
15255#define TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos)
15256#define TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk
15257#define TSC_IOASCR_G6_IO2_Pos (21U)
15258#define TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos)
15259#define TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk
15260#define TSC_IOASCR_G6_IO3_Pos (22U)
15261#define TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos)
15262#define TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk
15263#define TSC_IOASCR_G6_IO4_Pos (23U)
15264#define TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos)
15265#define TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk
15266#define TSC_IOASCR_G7_IO1_Pos (24U)
15267#define TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos)
15268#define TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk
15269#define TSC_IOASCR_G7_IO2_Pos (25U)
15270#define TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos)
15271#define TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk
15272#define TSC_IOASCR_G7_IO3_Pos (26U)
15273#define TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos)
15274#define TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk
15275#define TSC_IOASCR_G7_IO4_Pos (27U)
15276#define TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos)
15277#define TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk
15278#define TSC_IOASCR_G8_IO1_Pos (28U)
15279#define TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos)
15280#define TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk
15281#define TSC_IOASCR_G8_IO2_Pos (29U)
15282#define TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos)
15283#define TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk
15284#define TSC_IOASCR_G8_IO3_Pos (30U)
15285#define TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos)
15286#define TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk
15287#define TSC_IOASCR_G8_IO4_Pos (31U)
15288#define TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos)
15289#define TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk
15291/******************* Bit definition for TSC_IOSCR register ******************/
15292#define TSC_IOSCR_G1_IO1_Pos (0U)
15293#define TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos)
15294#define TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk
15295#define TSC_IOSCR_G1_IO2_Pos (1U)
15296#define TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos)
15297#define TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk
15298#define TSC_IOSCR_G1_IO3_Pos (2U)
15299#define TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos)
15300#define TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk
15301#define TSC_IOSCR_G1_IO4_Pos (3U)
15302#define TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos)
15303#define TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk
15304#define TSC_IOSCR_G2_IO1_Pos (4U)
15305#define TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos)
15306#define TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk
15307#define TSC_IOSCR_G2_IO2_Pos (5U)
15308#define TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos)
15309#define TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk
15310#define TSC_IOSCR_G2_IO3_Pos (6U)
15311#define TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos)
15312#define TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk
15313#define TSC_IOSCR_G2_IO4_Pos (7U)
15314#define TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos)
15315#define TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk
15316#define TSC_IOSCR_G3_IO1_Pos (8U)
15317#define TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos)
15318#define TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk
15319#define TSC_IOSCR_G3_IO2_Pos (9U)
15320#define TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos)
15321#define TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk
15322#define TSC_IOSCR_G3_IO3_Pos (10U)
15323#define TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos)
15324#define TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk
15325#define TSC_IOSCR_G3_IO4_Pos (11U)
15326#define TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos)
15327#define TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk
15328#define TSC_IOSCR_G4_IO1_Pos (12U)
15329#define TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos)
15330#define TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk
15331#define TSC_IOSCR_G4_IO2_Pos (13U)
15332#define TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos)
15333#define TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk
15334#define TSC_IOSCR_G4_IO3_Pos (14U)
15335#define TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos)
15336#define TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk
15337#define TSC_IOSCR_G4_IO4_Pos (15U)
15338#define TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos)
15339#define TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk
15340#define TSC_IOSCR_G5_IO1_Pos (16U)
15341#define TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos)
15342#define TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk
15343#define TSC_IOSCR_G5_IO2_Pos (17U)
15344#define TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos)
15345#define TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk
15346#define TSC_IOSCR_G5_IO3_Pos (18U)
15347#define TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos)
15348#define TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk
15349#define TSC_IOSCR_G5_IO4_Pos (19U)
15350#define TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos)
15351#define TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk
15352#define TSC_IOSCR_G6_IO1_Pos (20U)
15353#define TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos)
15354#define TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk
15355#define TSC_IOSCR_G6_IO2_Pos (21U)
15356#define TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos)
15357#define TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk
15358#define TSC_IOSCR_G6_IO3_Pos (22U)
15359#define TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos)
15360#define TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk
15361#define TSC_IOSCR_G6_IO4_Pos (23U)
15362#define TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos)
15363#define TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk
15364#define TSC_IOSCR_G7_IO1_Pos (24U)
15365#define TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos)
15366#define TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk
15367#define TSC_IOSCR_G7_IO2_Pos (25U)
15368#define TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos)
15369#define TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk
15370#define TSC_IOSCR_G7_IO3_Pos (26U)
15371#define TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos)
15372#define TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk
15373#define TSC_IOSCR_G7_IO4_Pos (27U)
15374#define TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos)
15375#define TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk
15376#define TSC_IOSCR_G8_IO1_Pos (28U)
15377#define TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos)
15378#define TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk
15379#define TSC_IOSCR_G8_IO2_Pos (29U)
15380#define TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos)
15381#define TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk
15382#define TSC_IOSCR_G8_IO3_Pos (30U)
15383#define TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos)
15384#define TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk
15385#define TSC_IOSCR_G8_IO4_Pos (31U)
15386#define TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos)
15387#define TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk
15389/******************* Bit definition for TSC_IOCCR register ******************/
15390#define TSC_IOCCR_G1_IO1_Pos (0U)
15391#define TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos)
15392#define TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk
15393#define TSC_IOCCR_G1_IO2_Pos (1U)
15394#define TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos)
15395#define TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk
15396#define TSC_IOCCR_G1_IO3_Pos (2U)
15397#define TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos)
15398#define TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk
15399#define TSC_IOCCR_G1_IO4_Pos (3U)
15400#define TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos)
15401#define TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk
15402#define TSC_IOCCR_G2_IO1_Pos (4U)
15403#define TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos)
15404#define TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk
15405#define TSC_IOCCR_G2_IO2_Pos (5U)
15406#define TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos)
15407#define TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk
15408#define TSC_IOCCR_G2_IO3_Pos (6U)
15409#define TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos)
15410#define TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk
15411#define TSC_IOCCR_G2_IO4_Pos (7U)
15412#define TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos)
15413#define TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk
15414#define TSC_IOCCR_G3_IO1_Pos (8U)
15415#define TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos)
15416#define TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk
15417#define TSC_IOCCR_G3_IO2_Pos (9U)
15418#define TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos)
15419#define TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk
15420#define TSC_IOCCR_G3_IO3_Pos (10U)
15421#define TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos)
15422#define TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk
15423#define TSC_IOCCR_G3_IO4_Pos (11U)
15424#define TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos)
15425#define TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk
15426#define TSC_IOCCR_G4_IO1_Pos (12U)
15427#define TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos)
15428#define TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk
15429#define TSC_IOCCR_G4_IO2_Pos (13U)
15430#define TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos)
15431#define TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk
15432#define TSC_IOCCR_G4_IO3_Pos (14U)
15433#define TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos)
15434#define TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk
15435#define TSC_IOCCR_G4_IO4_Pos (15U)
15436#define TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos)
15437#define TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk
15438#define TSC_IOCCR_G5_IO1_Pos (16U)
15439#define TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos)
15440#define TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk
15441#define TSC_IOCCR_G5_IO2_Pos (17U)
15442#define TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos)
15443#define TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk
15444#define TSC_IOCCR_G5_IO3_Pos (18U)
15445#define TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos)
15446#define TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk
15447#define TSC_IOCCR_G5_IO4_Pos (19U)
15448#define TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos)
15449#define TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk
15450#define TSC_IOCCR_G6_IO1_Pos (20U)
15451#define TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos)
15452#define TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk
15453#define TSC_IOCCR_G6_IO2_Pos (21U)
15454#define TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos)
15455#define TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk
15456#define TSC_IOCCR_G6_IO3_Pos (22U)
15457#define TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos)
15458#define TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk
15459#define TSC_IOCCR_G6_IO4_Pos (23U)
15460#define TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos)
15461#define TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk
15462#define TSC_IOCCR_G7_IO1_Pos (24U)
15463#define TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos)
15464#define TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk
15465#define TSC_IOCCR_G7_IO2_Pos (25U)
15466#define TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos)
15467#define TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk
15468#define TSC_IOCCR_G7_IO3_Pos (26U)
15469#define TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos)
15470#define TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk
15471#define TSC_IOCCR_G7_IO4_Pos (27U)
15472#define TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos)
15473#define TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk
15474#define TSC_IOCCR_G8_IO1_Pos (28U)
15475#define TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos)
15476#define TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk
15477#define TSC_IOCCR_G8_IO2_Pos (29U)
15478#define TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos)
15479#define TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk
15480#define TSC_IOCCR_G8_IO3_Pos (30U)
15481#define TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos)
15482#define TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk
15483#define TSC_IOCCR_G8_IO4_Pos (31U)
15484#define TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos)
15485#define TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk
15487/******************* Bit definition for TSC_IOGCSR register *****************/
15488#define TSC_IOGCSR_G1E_Pos (0U)
15489#define TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos)
15490#define TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk
15491#define TSC_IOGCSR_G2E_Pos (1U)
15492#define TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos)
15493#define TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk
15494#define TSC_IOGCSR_G3E_Pos (2U)
15495#define TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos)
15496#define TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk
15497#define TSC_IOGCSR_G4E_Pos (3U)
15498#define TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos)
15499#define TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk
15500#define TSC_IOGCSR_G5E_Pos (4U)
15501#define TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos)
15502#define TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk
15503#define TSC_IOGCSR_G6E_Pos (5U)
15504#define TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos)
15505#define TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk
15506#define TSC_IOGCSR_G7E_Pos (6U)
15507#define TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos)
15508#define TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk
15509#define TSC_IOGCSR_G8E_Pos (7U)
15510#define TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos)
15511#define TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk
15512#define TSC_IOGCSR_G1S_Pos (16U)
15513#define TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos)
15514#define TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk
15515#define TSC_IOGCSR_G2S_Pos (17U)
15516#define TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos)
15517#define TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk
15518#define TSC_IOGCSR_G3S_Pos (18U)
15519#define TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos)
15520#define TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk
15521#define TSC_IOGCSR_G4S_Pos (19U)
15522#define TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos)
15523#define TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk
15524#define TSC_IOGCSR_G5S_Pos (20U)
15525#define TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos)
15526#define TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk
15527#define TSC_IOGCSR_G6S_Pos (21U)
15528#define TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos)
15529#define TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk
15530#define TSC_IOGCSR_G7S_Pos (22U)
15531#define TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos)
15532#define TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk
15533#define TSC_IOGCSR_G8S_Pos (23U)
15534#define TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos)
15535#define TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk
15537/******************* Bit definition for TSC_IOGXCR register *****************/
15538#define TSC_IOGXCR_CNT_Pos (0U)
15539#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos)
15540#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk
15542/******************************************************************************/
15543/* */
15544/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
15545/* */
15546/******************************************************************************/
15547/****************** Bit definition for USART_CR1 register *******************/
15548#define USART_CR1_UE_Pos (0U)
15549#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
15550#define USART_CR1_UE USART_CR1_UE_Msk
15551#define USART_CR1_UESM_Pos (1U)
15552#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
15553#define USART_CR1_UESM USART_CR1_UESM_Msk
15554#define USART_CR1_RE_Pos (2U)
15555#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
15556#define USART_CR1_RE USART_CR1_RE_Msk
15557#define USART_CR1_TE_Pos (3U)
15558#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
15559#define USART_CR1_TE USART_CR1_TE_Msk
15560#define USART_CR1_IDLEIE_Pos (4U)
15561#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
15562#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
15563#define USART_CR1_RXNEIE_Pos (5U)
15564#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
15565#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
15566#define USART_CR1_TCIE_Pos (6U)
15567#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
15568#define USART_CR1_TCIE USART_CR1_TCIE_Msk
15569#define USART_CR1_TXEIE_Pos (7U)
15570#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
15571#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
15572#define USART_CR1_PEIE_Pos (8U)
15573#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
15574#define USART_CR1_PEIE USART_CR1_PEIE_Msk
15575#define USART_CR1_PS_Pos (9U)
15576#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
15577#define USART_CR1_PS USART_CR1_PS_Msk
15578#define USART_CR1_PCE_Pos (10U)
15579#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
15580#define USART_CR1_PCE USART_CR1_PCE_Msk
15581#define USART_CR1_WAKE_Pos (11U)
15582#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
15583#define USART_CR1_WAKE USART_CR1_WAKE_Msk
15584#define USART_CR1_M_Pos (12U)
15585#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
15586#define USART_CR1_M USART_CR1_M_Msk
15587#define USART_CR1_M0_Pos (12U)
15588#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
15589#define USART_CR1_M0 USART_CR1_M0_Msk
15590#define USART_CR1_MME_Pos (13U)
15591#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
15592#define USART_CR1_MME USART_CR1_MME_Msk
15593#define USART_CR1_CMIE_Pos (14U)
15594#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
15595#define USART_CR1_CMIE USART_CR1_CMIE_Msk
15596#define USART_CR1_OVER8_Pos (15U)
15597#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
15598#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
15599#define USART_CR1_DEDT_Pos (16U)
15600#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
15601#define USART_CR1_DEDT USART_CR1_DEDT_Msk
15602#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
15603#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
15604#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
15605#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
15606#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
15607#define USART_CR1_DEAT_Pos (21U)
15608#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
15609#define USART_CR1_DEAT USART_CR1_DEAT_Msk
15610#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
15611#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
15612#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
15613#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
15614#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
15615#define USART_CR1_RTOIE_Pos (26U)
15616#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
15617#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
15618#define USART_CR1_EOBIE_Pos (27U)
15619#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
15620#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
15621#define USART_CR1_M1_Pos (28U)
15622#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
15623#define USART_CR1_M1 USART_CR1_M1_Msk
15625/****************** Bit definition for USART_CR2 register *******************/
15626#define USART_CR2_ADDM7_Pos (4U)
15627#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
15628#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
15629#define USART_CR2_LBDL_Pos (5U)
15630#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
15631#define USART_CR2_LBDL USART_CR2_LBDL_Msk
15632#define USART_CR2_LBDIE_Pos (6U)
15633#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
15634#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
15635#define USART_CR2_LBCL_Pos (8U)
15636#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
15637#define USART_CR2_LBCL USART_CR2_LBCL_Msk
15638#define USART_CR2_CPHA_Pos (9U)
15639#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
15640#define USART_CR2_CPHA USART_CR2_CPHA_Msk
15641#define USART_CR2_CPOL_Pos (10U)
15642#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
15643#define USART_CR2_CPOL USART_CR2_CPOL_Msk
15644#define USART_CR2_CLKEN_Pos (11U)
15645#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
15646#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
15647#define USART_CR2_STOP_Pos (12U)
15648#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
15649#define USART_CR2_STOP USART_CR2_STOP_Msk
15650#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
15651#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
15652#define USART_CR2_LINEN_Pos (14U)
15653#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
15654#define USART_CR2_LINEN USART_CR2_LINEN_Msk
15655#define USART_CR2_SWAP_Pos (15U)
15656#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
15657#define USART_CR2_SWAP USART_CR2_SWAP_Msk
15658#define USART_CR2_RXINV_Pos (16U)
15659#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
15660#define USART_CR2_RXINV USART_CR2_RXINV_Msk
15661#define USART_CR2_TXINV_Pos (17U)
15662#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
15663#define USART_CR2_TXINV USART_CR2_TXINV_Msk
15664#define USART_CR2_DATAINV_Pos (18U)
15665#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
15666#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
15667#define USART_CR2_MSBFIRST_Pos (19U)
15668#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
15669#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
15670#define USART_CR2_ABREN_Pos (20U)
15671#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
15672#define USART_CR2_ABREN USART_CR2_ABREN_Msk
15673#define USART_CR2_ABRMODE_Pos (21U)
15674#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
15675#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
15676#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
15677#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
15678#define USART_CR2_RTOEN_Pos (23U)
15679#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
15680#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
15681#define USART_CR2_ADD_Pos (24U)
15682#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
15683#define USART_CR2_ADD USART_CR2_ADD_Msk
15685/****************** Bit definition for USART_CR3 register *******************/
15686#define USART_CR3_EIE_Pos (0U)
15687#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
15688#define USART_CR3_EIE USART_CR3_EIE_Msk
15689#define USART_CR3_IREN_Pos (1U)
15690#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
15691#define USART_CR3_IREN USART_CR3_IREN_Msk
15692#define USART_CR3_IRLP_Pos (2U)
15693#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
15694#define USART_CR3_IRLP USART_CR3_IRLP_Msk
15695#define USART_CR3_HDSEL_Pos (3U)
15696#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
15697#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
15698#define USART_CR3_NACK_Pos (4U)
15699#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
15700#define USART_CR3_NACK USART_CR3_NACK_Msk
15701#define USART_CR3_SCEN_Pos (5U)
15702#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
15703#define USART_CR3_SCEN USART_CR3_SCEN_Msk
15704#define USART_CR3_DMAR_Pos (6U)
15705#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
15706#define USART_CR3_DMAR USART_CR3_DMAR_Msk
15707#define USART_CR3_DMAT_Pos (7U)
15708#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
15709#define USART_CR3_DMAT USART_CR3_DMAT_Msk
15710#define USART_CR3_RTSE_Pos (8U)
15711#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
15712#define USART_CR3_RTSE USART_CR3_RTSE_Msk
15713#define USART_CR3_CTSE_Pos (9U)
15714#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
15715#define USART_CR3_CTSE USART_CR3_CTSE_Msk
15716#define USART_CR3_CTSIE_Pos (10U)
15717#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
15718#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
15719#define USART_CR3_ONEBIT_Pos (11U)
15720#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
15721#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
15722#define USART_CR3_OVRDIS_Pos (12U)
15723#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
15724#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
15725#define USART_CR3_DDRE_Pos (13U)
15726#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
15727#define USART_CR3_DDRE USART_CR3_DDRE_Msk
15728#define USART_CR3_DEM_Pos (14U)
15729#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
15730#define USART_CR3_DEM USART_CR3_DEM_Msk
15731#define USART_CR3_DEP_Pos (15U)
15732#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
15733#define USART_CR3_DEP USART_CR3_DEP_Msk
15734#define USART_CR3_SCARCNT_Pos (17U)
15735#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
15736#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
15737#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
15738#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
15739#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
15740#define USART_CR3_WUS_Pos (20U)
15741#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
15742#define USART_CR3_WUS USART_CR3_WUS_Msk
15743#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
15744#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
15745#define USART_CR3_WUFIE_Pos (22U)
15746#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
15747#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
15748#define USART_CR3_UCESM_Pos (23U)
15749#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos)
15750#define USART_CR3_UCESM USART_CR3_UCESM_Msk
15752/****************** Bit definition for USART_BRR register *******************/
15753#define USART_BRR_DIV_FRACTION_Pos (0U)
15754#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
15755#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
15756#define USART_BRR_DIV_MANTISSA_Pos (4U)
15757#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
15758#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
15760/****************** Bit definition for USART_GTPR register ******************/
15761#define USART_GTPR_PSC_Pos (0U)
15762#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
15763#define USART_GTPR_PSC USART_GTPR_PSC_Msk
15764#define USART_GTPR_GT_Pos (8U)
15765#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
15766#define USART_GTPR_GT USART_GTPR_GT_Msk
15768/******************* Bit definition for USART_RTOR register *****************/
15769#define USART_RTOR_RTO_Pos (0U)
15770#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
15771#define USART_RTOR_RTO USART_RTOR_RTO_Msk
15772#define USART_RTOR_BLEN_Pos (24U)
15773#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
15774#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
15776/******************* Bit definition for USART_RQR register ******************/
15777#define USART_RQR_ABRRQ_Pos (0U)
15778#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
15779#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
15780#define USART_RQR_SBKRQ_Pos (1U)
15781#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
15782#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
15783#define USART_RQR_MMRQ_Pos (2U)
15784#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
15785#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
15786#define USART_RQR_RXFRQ_Pos (3U)
15787#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
15788#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
15789#define USART_RQR_TXFRQ_Pos (4U)
15790#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
15791#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
15793/******************* Bit definition for USART_ISR register ******************/
15794#define USART_ISR_PE_Pos (0U)
15795#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
15796#define USART_ISR_PE USART_ISR_PE_Msk
15797#define USART_ISR_FE_Pos (1U)
15798#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
15799#define USART_ISR_FE USART_ISR_FE_Msk
15800#define USART_ISR_NE_Pos (2U)
15801#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
15802#define USART_ISR_NE USART_ISR_NE_Msk
15803#define USART_ISR_ORE_Pos (3U)
15804#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
15805#define USART_ISR_ORE USART_ISR_ORE_Msk
15806#define USART_ISR_IDLE_Pos (4U)
15807#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
15808#define USART_ISR_IDLE USART_ISR_IDLE_Msk
15809#define USART_ISR_RXNE_Pos (5U)
15810#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
15811#define USART_ISR_RXNE USART_ISR_RXNE_Msk
15812#define USART_ISR_TC_Pos (6U)
15813#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
15814#define USART_ISR_TC USART_ISR_TC_Msk
15815#define USART_ISR_TXE_Pos (7U)
15816#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
15817#define USART_ISR_TXE USART_ISR_TXE_Msk
15818#define USART_ISR_LBDF_Pos (8U)
15819#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
15820#define USART_ISR_LBDF USART_ISR_LBDF_Msk
15821#define USART_ISR_CTSIF_Pos (9U)
15822#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
15823#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
15824#define USART_ISR_CTS_Pos (10U)
15825#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
15826#define USART_ISR_CTS USART_ISR_CTS_Msk
15827#define USART_ISR_RTOF_Pos (11U)
15828#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
15829#define USART_ISR_RTOF USART_ISR_RTOF_Msk
15830#define USART_ISR_EOBF_Pos (12U)
15831#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
15832#define USART_ISR_EOBF USART_ISR_EOBF_Msk
15833#define USART_ISR_ABRE_Pos (14U)
15834#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
15835#define USART_ISR_ABRE USART_ISR_ABRE_Msk
15836#define USART_ISR_ABRF_Pos (15U)
15837#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
15838#define USART_ISR_ABRF USART_ISR_ABRF_Msk
15839#define USART_ISR_BUSY_Pos (16U)
15840#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
15841#define USART_ISR_BUSY USART_ISR_BUSY_Msk
15842#define USART_ISR_CMF_Pos (17U)
15843#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
15844#define USART_ISR_CMF USART_ISR_CMF_Msk
15845#define USART_ISR_SBKF_Pos (18U)
15846#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
15847#define USART_ISR_SBKF USART_ISR_SBKF_Msk
15848#define USART_ISR_RWU_Pos (19U)
15849#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
15850#define USART_ISR_RWU USART_ISR_RWU_Msk
15851#define USART_ISR_WUF_Pos (20U)
15852#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
15853#define USART_ISR_WUF USART_ISR_WUF_Msk
15854#define USART_ISR_TEACK_Pos (21U)
15855#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
15856#define USART_ISR_TEACK USART_ISR_TEACK_Msk
15857#define USART_ISR_REACK_Pos (22U)
15858#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
15859#define USART_ISR_REACK USART_ISR_REACK_Msk
15861/******************* Bit definition for USART_ICR register ******************/
15862#define USART_ICR_PECF_Pos (0U)
15863#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
15864#define USART_ICR_PECF USART_ICR_PECF_Msk
15865#define USART_ICR_FECF_Pos (1U)
15866#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
15867#define USART_ICR_FECF USART_ICR_FECF_Msk
15868#define USART_ICR_NECF_Pos (2U)
15869#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
15870#define USART_ICR_NECF USART_ICR_NECF_Msk
15871#define USART_ICR_ORECF_Pos (3U)
15872#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
15873#define USART_ICR_ORECF USART_ICR_ORECF_Msk
15874#define USART_ICR_IDLECF_Pos (4U)
15875#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
15876#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
15877#define USART_ICR_TCCF_Pos (6U)
15878#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
15879#define USART_ICR_TCCF USART_ICR_TCCF_Msk
15880#define USART_ICR_LBDCF_Pos (8U)
15881#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
15882#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
15883#define USART_ICR_CTSCF_Pos (9U)
15884#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
15885#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
15886#define USART_ICR_RTOCF_Pos (11U)
15887#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
15888#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
15889#define USART_ICR_EOBCF_Pos (12U)
15890#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
15891#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
15892#define USART_ICR_CMCF_Pos (17U)
15893#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
15894#define USART_ICR_CMCF USART_ICR_CMCF_Msk
15895#define USART_ICR_WUCF_Pos (20U)
15896#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
15897#define USART_ICR_WUCF USART_ICR_WUCF_Msk
15899/* Legacy defines */
15900#define USART_ICR_NCF_Pos USART_ICR_NECF_Pos
15901#define USART_ICR_NCF_Msk USART_ICR_NECF_Msk
15902#define USART_ICR_NCF USART_ICR_NECF
15903
15904/******************* Bit definition for USART_RDR register ******************/
15905#define USART_RDR_RDR_Pos (0U)
15906#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
15907#define USART_RDR_RDR USART_RDR_RDR_Msk
15909/******************* Bit definition for USART_TDR register ******************/
15910#define USART_TDR_TDR_Pos (0U)
15911#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
15912#define USART_TDR_TDR USART_TDR_TDR_Msk
15914/******************************************************************************/
15915/* */
15916/* Single Wire Protocol Master Interface (SWPMI) */
15917/* */
15918/******************************************************************************/
15919
15920/******************* Bit definition for SWPMI_CR register ********************/
15921#define SWPMI_CR_RXDMA_Pos (0U)
15922#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
15923#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
15924#define SWPMI_CR_TXDMA_Pos (1U)
15925#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
15926#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
15927#define SWPMI_CR_RXMODE_Pos (2U)
15928#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
15929#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
15930#define SWPMI_CR_TXMODE_Pos (3U)
15931#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
15932#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
15933#define SWPMI_CR_LPBK_Pos (4U)
15934#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
15935#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
15936#define SWPMI_CR_SWPACT_Pos (5U)
15937#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
15938#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
15939#define SWPMI_CR_DEACT_Pos (10U)
15940#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
15941#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
15943/******************* Bit definition for SWPMI_BRR register ********************/
15944#define SWPMI_BRR_BR_Pos (0U)
15945#define SWPMI_BRR_BR_Msk (0x3FUL << SWPMI_BRR_BR_Pos)
15946#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
15948/******************* Bit definition for SWPMI_ISR register ********************/
15949#define SWPMI_ISR_RXBFF_Pos (0U)
15950#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
15951#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
15952#define SWPMI_ISR_TXBEF_Pos (1U)
15953#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
15954#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
15955#define SWPMI_ISR_RXBERF_Pos (2U)
15956#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
15957#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
15958#define SWPMI_ISR_RXOVRF_Pos (3U)
15959#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
15960#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
15961#define SWPMI_ISR_TXUNRF_Pos (4U)
15962#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
15963#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
15964#define SWPMI_ISR_RXNE_Pos (5U)
15965#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
15966#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
15967#define SWPMI_ISR_TXE_Pos (6U)
15968#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
15969#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
15970#define SWPMI_ISR_TCF_Pos (7U)
15971#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
15972#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
15973#define SWPMI_ISR_SRF_Pos (8U)
15974#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
15975#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
15976#define SWPMI_ISR_SUSP_Pos (9U)
15977#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
15978#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
15979#define SWPMI_ISR_DEACTF_Pos (10U)
15980#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
15981#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
15983/******************* Bit definition for SWPMI_ICR register ********************/
15984#define SWPMI_ICR_CRXBFF_Pos (0U)
15985#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
15986#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
15987#define SWPMI_ICR_CTXBEF_Pos (1U)
15988#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
15989#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
15990#define SWPMI_ICR_CRXBERF_Pos (2U)
15991#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
15992#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
15993#define SWPMI_ICR_CRXOVRF_Pos (3U)
15994#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
15995#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
15996#define SWPMI_ICR_CTXUNRF_Pos (4U)
15997#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
15998#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
15999#define SWPMI_ICR_CTCF_Pos (7U)
16000#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
16001#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
16002#define SWPMI_ICR_CSRF_Pos (8U)
16003#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
16004#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
16006/******************* Bit definition for SWPMI_IER register ********************/
16007#define SWPMI_IER_SRIE_Pos (8U)
16008#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
16009#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
16010#define SWPMI_IER_TCIE_Pos (7U)
16011#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
16012#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
16013#define SWPMI_IER_TIE_Pos (6U)
16014#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
16015#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
16016#define SWPMI_IER_RIE_Pos (5U)
16017#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
16018#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
16019#define SWPMI_IER_TXUNRIE_Pos (4U)
16020#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
16021#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
16022#define SWPMI_IER_RXOVRIE_Pos (3U)
16023#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
16024#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
16025#define SWPMI_IER_RXBERIE_Pos (2U)
16026#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
16027#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
16028#define SWPMI_IER_TXBEIE_Pos (1U)
16029#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
16030#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
16031#define SWPMI_IER_RXBFIE_Pos (0U)
16032#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
16033#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
16035/******************* Bit definition for SWPMI_RFL register ********************/
16036#define SWPMI_RFL_RFL_Pos (0U)
16037#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
16038#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
16039#define SWPMI_RFL_RFL_0_1_Pos (0U)
16040#define SWPMI_RFL_RFL_0_1_Msk (0x3UL << SWPMI_RFL_RFL_0_1_Pos)
16041#define SWPMI_RFL_RFL_0_1 SWPMI_RFL_RFL_0_1_Msk
16043/******************* Bit definition for SWPMI_TDR register ********************/
16044#define SWPMI_TDR_TD_Pos (0U)
16045#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
16046#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
16048/******************* Bit definition for SWPMI_RDR register ********************/
16049#define SWPMI_RDR_RD_Pos (0U)
16050#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
16051#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
16053/******************* Bit definition for SWPMI_OR register ********************/
16054#define SWPMI_OR_TBYP_Pos (0U)
16055#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
16056#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
16057#define SWPMI_OR_CLASS_Pos (1U)
16058#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
16059#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
16061/******************************************************************************/
16062/* */
16063/* VREFBUF */
16064/* */
16065/******************************************************************************/
16066/******************* Bit definition for VREFBUF_CSR register ****************/
16067#define VREFBUF_CSR_ENVR_Pos (0U)
16068#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
16069#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
16070#define VREFBUF_CSR_HIZ_Pos (1U)
16071#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
16072#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
16073#define VREFBUF_CSR_VRS_Pos (2U)
16074#define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos)
16075#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
16076#define VREFBUF_CSR_VRR_Pos (3U)
16077#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
16078#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
16080/******************* Bit definition for VREFBUF_CCR register ******************/
16081#define VREFBUF_CCR_TRIM_Pos (0U)
16082#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
16083#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
16085/******************************************************************************/
16086/* */
16087/* Window WATCHDOG */
16088/* */
16089/******************************************************************************/
16090/******************* Bit definition for WWDG_CR register ********************/
16091#define WWDG_CR_T_Pos (0U)
16092#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
16093#define WWDG_CR_T WWDG_CR_T_Msk
16094#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
16095#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
16096#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
16097#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
16098#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
16099#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
16100#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
16102#define WWDG_CR_WDGA_Pos (7U)
16103#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
16104#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
16106/******************* Bit definition for WWDG_CFR register *******************/
16107#define WWDG_CFR_W_Pos (0U)
16108#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
16109#define WWDG_CFR_W WWDG_CFR_W_Msk
16110#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
16111#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
16112#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
16113#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
16114#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
16115#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
16116#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
16118#define WWDG_CFR_WDGTB_Pos (7U)
16119#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
16120#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
16121#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
16122#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
16124#define WWDG_CFR_EWI_Pos (9U)
16125#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
16126#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
16128/******************* Bit definition for WWDG_SR register ********************/
16129#define WWDG_SR_EWIF_Pos (0U)
16130#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
16131#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
16134/******************************************************************************/
16135/* */
16136/* Debug MCU */
16137/* */
16138/******************************************************************************/
16139/******************** Bit definition for DBGMCU_IDCODE register *************/
16140#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
16141#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
16142#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
16143#define DBGMCU_IDCODE_REV_ID_Pos (16U)
16144#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
16145#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
16146
16147/******************** Bit definition for DBGMCU_CR register *****************/
16148#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
16149#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
16150#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
16151#define DBGMCU_CR_DBG_STOP_Pos (1U)
16152#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
16153#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
16154#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
16155#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
16156#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
16157#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
16158#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
16159#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
16160
16161#define DBGMCU_CR_TRACE_MODE_Pos (6U)
16162#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
16163#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
16164#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
16165#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
16167/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
16168#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
16169#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)
16170#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
16171#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
16172#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)
16173#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
16174#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
16175#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)
16176#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
16177#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
16178#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)
16179#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
16180#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
16181#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)
16182#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
16183#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
16184#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)
16185#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
16186#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
16187#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)
16188#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
16189#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
16190#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)
16191#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
16192#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
16193#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)
16194#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
16195#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
16196#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)
16197#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
16198#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
16199#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)
16200#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
16201#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (23U)
16202#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)
16203#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
16204#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos (25U)
16205#define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos)
16206#define DBGMCU_APB1FZR1_DBG_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
16207#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
16208#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)
16209#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
16210
16211/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
16212#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U)
16213#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)
16214#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
16215
16216/******************** Bit definition for DBGMCU_APB2FZ register ************/
16217#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
16218#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)
16219#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
16220#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
16221#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)
16222#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
16223#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
16224#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)
16225#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
16226#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
16227#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)
16228#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
16229#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
16230#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)
16231#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
16232
16233
16246/******************************* ADC Instances ********************************/
16247#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
16248 ((INSTANCE) == ADC2) || \
16249 ((INSTANCE) == ADC3))
16250
16251#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
16252
16253#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
16254
16255/******************************** CAN Instances ******************************/
16256#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
16257
16258/******************************** COMP Instances ******************************/
16259#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
16260 ((INSTANCE) == COMP2))
16261
16262#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
16263
16264/******************** COMP Instances with window mode capability **************/
16265#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
16266
16267/******************************* CRC Instances ********************************/
16268#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
16269
16270/******************************* DAC Instances ********************************/
16271#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
16272
16273/****************************** DFSDM Instances *******************************/
16274#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
16275 ((INSTANCE) == DFSDM1_Filter1) || \
16276 ((INSTANCE) == DFSDM1_Filter2) || \
16277 ((INSTANCE) == DFSDM1_Filter3))
16278
16279#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
16280 ((INSTANCE) == DFSDM1_Channel1) || \
16281 ((INSTANCE) == DFSDM1_Channel2) || \
16282 ((INSTANCE) == DFSDM1_Channel3) || \
16283 ((INSTANCE) == DFSDM1_Channel4) || \
16284 ((INSTANCE) == DFSDM1_Channel5) || \
16285 ((INSTANCE) == DFSDM1_Channel6) || \
16286 ((INSTANCE) == DFSDM1_Channel7))
16287
16288/******************************** DMA Instances *******************************/
16289#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
16290 ((INSTANCE) == DMA1_Channel2) || \
16291 ((INSTANCE) == DMA1_Channel3) || \
16292 ((INSTANCE) == DMA1_Channel4) || \
16293 ((INSTANCE) == DMA1_Channel5) || \
16294 ((INSTANCE) == DMA1_Channel6) || \
16295 ((INSTANCE) == DMA1_Channel7) || \
16296 ((INSTANCE) == DMA2_Channel1) || \
16297 ((INSTANCE) == DMA2_Channel2) || \
16298 ((INSTANCE) == DMA2_Channel3) || \
16299 ((INSTANCE) == DMA2_Channel4) || \
16300 ((INSTANCE) == DMA2_Channel5) || \
16301 ((INSTANCE) == DMA2_Channel6) || \
16302 ((INSTANCE) == DMA2_Channel7))
16303
16304/******************************* GPIO Instances *******************************/
16305#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
16306 ((INSTANCE) == GPIOB) || \
16307 ((INSTANCE) == GPIOC) || \
16308 ((INSTANCE) == GPIOD) || \
16309 ((INSTANCE) == GPIOE) || \
16310 ((INSTANCE) == GPIOF) || \
16311 ((INSTANCE) == GPIOG) || \
16312 ((INSTANCE) == GPIOH))
16313
16314/******************************* GPIO AF Instances ****************************/
16315/* On L4, all GPIO Bank support AF */
16316#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
16317
16318/**************************** GPIO Lock Instances *****************************/
16319/* On L4, all GPIO Bank support the Lock mechanism */
16320#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
16321
16322/******************************** I2C Instances *******************************/
16323#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
16324 ((INSTANCE) == I2C2) || \
16325 ((INSTANCE) == I2C3))
16326
16327/****************** I2C Instances : wakeup capability from stop modes *********/
16328#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
16329
16330/****************************** OPAMP Instances *******************************/
16331#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
16332 ((INSTANCE) == OPAMP2))
16333
16334#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
16335
16336/******************************* QSPI Instances *******************************/
16337#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
16338
16339/******************************* RNG Instances ********************************/
16340#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
16341
16342/****************************** RTC Instances *********************************/
16343#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
16344
16345/******************************** SAI Instances *******************************/
16346#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
16347 ((INSTANCE) == SAI1_Block_B) || \
16348 ((INSTANCE) == SAI2_Block_A) || \
16349 ((INSTANCE) == SAI2_Block_B))
16350
16351/****************************** SDMMC Instances *******************************/
16352#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
16353
16354/****************************** SMBUS Instances *******************************/
16355#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
16356 ((INSTANCE) == I2C2) || \
16357 ((INSTANCE) == I2C3))
16358
16359/******************************** SPI Instances *******************************/
16360#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
16361 ((INSTANCE) == SPI2) || \
16362 ((INSTANCE) == SPI3))
16363
16364/******************************** SWPMI Instances *****************************/
16365#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
16366
16367/****************** LPTIM Instances : All supported instances *****************/
16368#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
16369 ((INSTANCE) == LPTIM2))
16370
16371/****************** LPTIM Instances : supporting the encoder mode *************/
16372#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
16373
16374/****************** TIM Instances : All supported instances *******************/
16375#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16376 ((INSTANCE) == TIM2) || \
16377 ((INSTANCE) == TIM3) || \
16378 ((INSTANCE) == TIM4) || \
16379 ((INSTANCE) == TIM5) || \
16380 ((INSTANCE) == TIM6) || \
16381 ((INSTANCE) == TIM7) || \
16382 ((INSTANCE) == TIM8) || \
16383 ((INSTANCE) == TIM15) || \
16384 ((INSTANCE) == TIM16) || \
16385 ((INSTANCE) == TIM17))
16386
16387/****************** TIM Instances : supporting 32 bits counter ****************/
16388#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
16389 ((INSTANCE) == TIM5))
16390
16391/****************** TIM Instances : supporting the break function *************/
16392#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16393 ((INSTANCE) == TIM8) || \
16394 ((INSTANCE) == TIM15) || \
16395 ((INSTANCE) == TIM16) || \
16396 ((INSTANCE) == TIM17))
16397
16398/************** TIM Instances : supporting Break source selection *************/
16399#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16400 ((INSTANCE) == TIM8) || \
16401 ((INSTANCE) == TIM15) || \
16402 ((INSTANCE) == TIM16) || \
16403 ((INSTANCE) == TIM17))
16404
16405/****************** TIM Instances : supporting 2 break inputs *****************/
16406#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16407 ((INSTANCE) == TIM8))
16408
16409/************* TIM Instances : at least 1 capture/compare channel *************/
16410#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16411 ((INSTANCE) == TIM2) || \
16412 ((INSTANCE) == TIM3) || \
16413 ((INSTANCE) == TIM4) || \
16414 ((INSTANCE) == TIM5) || \
16415 ((INSTANCE) == TIM8) || \
16416 ((INSTANCE) == TIM15) || \
16417 ((INSTANCE) == TIM16) || \
16418 ((INSTANCE) == TIM17))
16419
16420/************ TIM Instances : at least 2 capture/compare channels *************/
16421#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16422 ((INSTANCE) == TIM2) || \
16423 ((INSTANCE) == TIM3) || \
16424 ((INSTANCE) == TIM4) || \
16425 ((INSTANCE) == TIM5) || \
16426 ((INSTANCE) == TIM8) || \
16427 ((INSTANCE) == TIM15))
16428
16429/************ TIM Instances : at least 3 capture/compare channels *************/
16430#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16431 ((INSTANCE) == TIM2) || \
16432 ((INSTANCE) == TIM3) || \
16433 ((INSTANCE) == TIM4) || \
16434 ((INSTANCE) == TIM5) || \
16435 ((INSTANCE) == TIM8))
16436
16437/************ TIM Instances : at least 4 capture/compare channels *************/
16438#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16439 ((INSTANCE) == TIM2) || \
16440 ((INSTANCE) == TIM3) || \
16441 ((INSTANCE) == TIM4) || \
16442 ((INSTANCE) == TIM5) || \
16443 ((INSTANCE) == TIM8))
16444
16445/****************** TIM Instances : at least 5 capture/compare channels *******/
16446#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16447 ((INSTANCE) == TIM8))
16448
16449/****************** TIM Instances : at least 6 capture/compare channels *******/
16450#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16451 ((INSTANCE) == TIM8))
16452
16453/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
16454#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16455 ((INSTANCE) == TIM8) || \
16456 ((INSTANCE) == TIM15) || \
16457 ((INSTANCE) == TIM16) || \
16458 ((INSTANCE) == TIM17))
16459
16460/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
16461#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16462 ((INSTANCE) == TIM2) || \
16463 ((INSTANCE) == TIM3) || \
16464 ((INSTANCE) == TIM4) || \
16465 ((INSTANCE) == TIM5) || \
16466 ((INSTANCE) == TIM6) || \
16467 ((INSTANCE) == TIM7) || \
16468 ((INSTANCE) == TIM8) || \
16469 ((INSTANCE) == TIM15) || \
16470 ((INSTANCE) == TIM16) || \
16471 ((INSTANCE) == TIM17))
16472
16473/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
16474#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16475 ((INSTANCE) == TIM2) || \
16476 ((INSTANCE) == TIM3) || \
16477 ((INSTANCE) == TIM4) || \
16478 ((INSTANCE) == TIM5) || \
16479 ((INSTANCE) == TIM8) || \
16480 ((INSTANCE) == TIM15) || \
16481 ((INSTANCE) == TIM16) || \
16482 ((INSTANCE) == TIM17))
16483
16484/******************** TIM Instances : DMA burst feature ***********************/
16485#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16486 ((INSTANCE) == TIM2) || \
16487 ((INSTANCE) == TIM3) || \
16488 ((INSTANCE) == TIM4) || \
16489 ((INSTANCE) == TIM5) || \
16490 ((INSTANCE) == TIM8) || \
16491 ((INSTANCE) == TIM15) || \
16492 ((INSTANCE) == TIM16) || \
16493 ((INSTANCE) == TIM17))
16494
16495/******************* TIM Instances : output(s) available **********************/
16496#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
16497 ((((INSTANCE) == TIM1) && \
16498 (((CHANNEL) == TIM_CHANNEL_1) || \
16499 ((CHANNEL) == TIM_CHANNEL_2) || \
16500 ((CHANNEL) == TIM_CHANNEL_3) || \
16501 ((CHANNEL) == TIM_CHANNEL_4) || \
16502 ((CHANNEL) == TIM_CHANNEL_5) || \
16503 ((CHANNEL) == TIM_CHANNEL_6))) \
16504 || \
16505 (((INSTANCE) == TIM2) && \
16506 (((CHANNEL) == TIM_CHANNEL_1) || \
16507 ((CHANNEL) == TIM_CHANNEL_2) || \
16508 ((CHANNEL) == TIM_CHANNEL_3) || \
16509 ((CHANNEL) == TIM_CHANNEL_4))) \
16510 || \
16511 (((INSTANCE) == TIM3) && \
16512 (((CHANNEL) == TIM_CHANNEL_1) || \
16513 ((CHANNEL) == TIM_CHANNEL_2) || \
16514 ((CHANNEL) == TIM_CHANNEL_3) || \
16515 ((CHANNEL) == TIM_CHANNEL_4))) \
16516 || \
16517 (((INSTANCE) == TIM4) && \
16518 (((CHANNEL) == TIM_CHANNEL_1) || \
16519 ((CHANNEL) == TIM_CHANNEL_2) || \
16520 ((CHANNEL) == TIM_CHANNEL_3) || \
16521 ((CHANNEL) == TIM_CHANNEL_4))) \
16522 || \
16523 (((INSTANCE) == TIM5) && \
16524 (((CHANNEL) == TIM_CHANNEL_1) || \
16525 ((CHANNEL) == TIM_CHANNEL_2) || \
16526 ((CHANNEL) == TIM_CHANNEL_3) || \
16527 ((CHANNEL) == TIM_CHANNEL_4))) \
16528 || \
16529 (((INSTANCE) == TIM8) && \
16530 (((CHANNEL) == TIM_CHANNEL_1) || \
16531 ((CHANNEL) == TIM_CHANNEL_2) || \
16532 ((CHANNEL) == TIM_CHANNEL_3) || \
16533 ((CHANNEL) == TIM_CHANNEL_4) || \
16534 ((CHANNEL) == TIM_CHANNEL_5) || \
16535 ((CHANNEL) == TIM_CHANNEL_6))) \
16536 || \
16537 (((INSTANCE) == TIM15) && \
16538 (((CHANNEL) == TIM_CHANNEL_1) || \
16539 ((CHANNEL) == TIM_CHANNEL_2))) \
16540 || \
16541 (((INSTANCE) == TIM16) && \
16542 (((CHANNEL) == TIM_CHANNEL_1))) \
16543 || \
16544 (((INSTANCE) == TIM17) && \
16545 (((CHANNEL) == TIM_CHANNEL_1))))
16546
16547/****************** TIM Instances : supporting complementary output(s) ********/
16548#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
16549 ((((INSTANCE) == TIM1) && \
16550 (((CHANNEL) == TIM_CHANNEL_1) || \
16551 ((CHANNEL) == TIM_CHANNEL_2) || \
16552 ((CHANNEL) == TIM_CHANNEL_3))) \
16553 || \
16554 (((INSTANCE) == TIM8) && \
16555 (((CHANNEL) == TIM_CHANNEL_1) || \
16556 ((CHANNEL) == TIM_CHANNEL_2) || \
16557 ((CHANNEL) == TIM_CHANNEL_3))) \
16558 || \
16559 (((INSTANCE) == TIM15) && \
16560 ((CHANNEL) == TIM_CHANNEL_1)) \
16561 || \
16562 (((INSTANCE) == TIM16) && \
16563 ((CHANNEL) == TIM_CHANNEL_1)) \
16564 || \
16565 (((INSTANCE) == TIM17) && \
16566 ((CHANNEL) == TIM_CHANNEL_1)))
16567
16568/****************** TIM Instances : supporting clock division *****************/
16569#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16570 ((INSTANCE) == TIM2) || \
16571 ((INSTANCE) == TIM3) || \
16572 ((INSTANCE) == TIM4) || \
16573 ((INSTANCE) == TIM5) || \
16574 ((INSTANCE) == TIM8) || \
16575 ((INSTANCE) == TIM15) || \
16576 ((INSTANCE) == TIM16) || \
16577 ((INSTANCE) == TIM17))
16578
16579/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
16580#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16581 ((INSTANCE) == TIM2) || \
16582 ((INSTANCE) == TIM3) || \
16583 ((INSTANCE) == TIM4) || \
16584 ((INSTANCE) == TIM5) || \
16585 ((INSTANCE) == TIM8) || \
16586 ((INSTANCE) == TIM15))
16587
16588/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
16589#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16590 ((INSTANCE) == TIM2) || \
16591 ((INSTANCE) == TIM3) || \
16592 ((INSTANCE) == TIM4) || \
16593 ((INSTANCE) == TIM5) || \
16594 ((INSTANCE) == TIM8))
16595
16596/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
16597#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16598 ((INSTANCE) == TIM2) || \
16599 ((INSTANCE) == TIM3) || \
16600 ((INSTANCE) == TIM4) || \
16601 ((INSTANCE) == TIM5) || \
16602 ((INSTANCE) == TIM8) || \
16603 ((INSTANCE) == TIM15))
16604
16605/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
16606#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16607 ((INSTANCE) == TIM2) || \
16608 ((INSTANCE) == TIM3) || \
16609 ((INSTANCE) == TIM4) || \
16610 ((INSTANCE) == TIM5) || \
16611 ((INSTANCE) == TIM8) || \
16612 ((INSTANCE) == TIM15))
16613
16614/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
16615#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16616 ((INSTANCE) == TIM8))
16617
16618/****************** TIM Instances : supporting commutation event generation ***/
16619#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16620 ((INSTANCE) == TIM8) || \
16621 ((INSTANCE) == TIM15) || \
16622 ((INSTANCE) == TIM16) || \
16623 ((INSTANCE) == TIM17))
16624
16625/****************** TIM Instances : supporting counting mode selection ********/
16626#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16627 ((INSTANCE) == TIM2) || \
16628 ((INSTANCE) == TIM3) || \
16629 ((INSTANCE) == TIM4) || \
16630 ((INSTANCE) == TIM5) || \
16631 ((INSTANCE) == TIM8))
16632
16633/****************** TIM Instances : supporting encoder interface **************/
16634#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16635 ((INSTANCE) == TIM2) || \
16636 ((INSTANCE) == TIM3) || \
16637 ((INSTANCE) == TIM4) || \
16638 ((INSTANCE) == TIM5) || \
16639 ((INSTANCE) == TIM8))
16640
16641/****************** TIM Instances : supporting Hall sensor interface **********/
16642#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16643 ((INSTANCE) == TIM2) || \
16644 ((INSTANCE) == TIM3) || \
16645 ((INSTANCE) == TIM4) || \
16646 ((INSTANCE) == TIM5) || \
16647 ((INSTANCE) == TIM8))
16648
16649/**************** TIM Instances : external trigger input available ************/
16650#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16651 ((INSTANCE) == TIM2) || \
16652 ((INSTANCE) == TIM3) || \
16653 ((INSTANCE) == TIM4) || \
16654 ((INSTANCE) == TIM5) || \
16655 ((INSTANCE) == TIM8))
16656
16657/************* TIM Instances : supporting ETR source selection ***************/
16658#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16659 ((INSTANCE) == TIM2) || \
16660 ((INSTANCE) == TIM3) || \
16661 ((INSTANCE) == TIM8))
16662
16663/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
16664#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16665 ((INSTANCE) == TIM2) || \
16666 ((INSTANCE) == TIM3) || \
16667 ((INSTANCE) == TIM4) || \
16668 ((INSTANCE) == TIM5) || \
16669 ((INSTANCE) == TIM6) || \
16670 ((INSTANCE) == TIM7) || \
16671 ((INSTANCE) == TIM8) || \
16672 ((INSTANCE) == TIM15))
16673
16674/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
16675#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16676 ((INSTANCE) == TIM2) || \
16677 ((INSTANCE) == TIM3) || \
16678 ((INSTANCE) == TIM4) || \
16679 ((INSTANCE) == TIM5) || \
16680 ((INSTANCE) == TIM8) || \
16681 ((INSTANCE) == TIM15))
16682
16683/****************** TIM Instances : supporting OCxREF clear *******************/
16684#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16685 ((INSTANCE) == TIM2) || \
16686 ((INSTANCE) == TIM3) || \
16687 ((INSTANCE) == TIM4) || \
16688 ((INSTANCE) == TIM5) || \
16689 ((INSTANCE) == TIM8))
16690
16691/****************** TIM Instances : remapping capability **********************/
16692#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16693 ((INSTANCE) == TIM2) || \
16694 ((INSTANCE) == TIM3) || \
16695 ((INSTANCE) == TIM8) || \
16696 ((INSTANCE) == TIM15) || \
16697 ((INSTANCE) == TIM16) || \
16698 ((INSTANCE) == TIM17))
16699
16700/****************** TIM Instances : supporting repetition counter *************/
16701#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16702 ((INSTANCE) == TIM8) || \
16703 ((INSTANCE) == TIM15) || \
16704 ((INSTANCE) == TIM16) || \
16705 ((INSTANCE) == TIM17))
16706
16707/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
16708#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16709 ((INSTANCE) == TIM8))
16710
16711/******************* TIM Instances : Timer input XOR function *****************/
16712#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16713 ((INSTANCE) == TIM2) || \
16714 ((INSTANCE) == TIM3) || \
16715 ((INSTANCE) == TIM4) || \
16716 ((INSTANCE) == TIM5) || \
16717 ((INSTANCE) == TIM8) || \
16718 ((INSTANCE) == TIM15))
16719
16720/****************** TIM Instances : Advanced timer instances *******************/
16721#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
16722 ((INSTANCE) == TIM8))
16723
16724/****************************** TSC Instances *********************************/
16725#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
16726
16727/******************** USART Instances : Synchronous mode **********************/
16728#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16729 ((INSTANCE) == USART2) || \
16730 ((INSTANCE) == USART3))
16731
16732/******************** UART Instances : Asynchronous mode **********************/
16733#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16734 ((INSTANCE) == USART2) || \
16735 ((INSTANCE) == USART3) || \
16736 ((INSTANCE) == UART4) || \
16737 ((INSTANCE) == UART5))
16738
16739/****************** UART Instances : Auto Baud Rate detection ****************/
16740#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16741 ((INSTANCE) == USART2) || \
16742 ((INSTANCE) == USART3) || \
16743 ((INSTANCE) == UART4) || \
16744 ((INSTANCE) == UART5))
16745
16746/****************** UART Instances : Driver Enable *****************/
16747#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16748 ((INSTANCE) == USART2) || \
16749 ((INSTANCE) == USART3) || \
16750 ((INSTANCE) == UART4) || \
16751 ((INSTANCE) == UART5) || \
16752 ((INSTANCE) == LPUART1))
16753
16754/******************** UART Instances : Half-Duplex mode **********************/
16755#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16756 ((INSTANCE) == USART2) || \
16757 ((INSTANCE) == USART3) || \
16758 ((INSTANCE) == UART4) || \
16759 ((INSTANCE) == UART5) || \
16760 ((INSTANCE) == LPUART1))
16761
16762/****************** UART Instances : Hardware Flow control ********************/
16763#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16764 ((INSTANCE) == USART2) || \
16765 ((INSTANCE) == USART3) || \
16766 ((INSTANCE) == UART4) || \
16767 ((INSTANCE) == UART5) || \
16768 ((INSTANCE) == LPUART1))
16769
16770/******************** UART Instances : LIN mode **********************/
16771#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16772 ((INSTANCE) == USART2) || \
16773 ((INSTANCE) == USART3) || \
16774 ((INSTANCE) == UART4) || \
16775 ((INSTANCE) == UART5))
16776
16777/******************** UART Instances : Wake-up from Stop mode **********************/
16778#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16779 ((INSTANCE) == USART2) || \
16780 ((INSTANCE) == USART3) || \
16781 ((INSTANCE) == UART4) || \
16782 ((INSTANCE) == UART5) || \
16783 ((INSTANCE) == LPUART1))
16784
16785/*********************** UART Instances : IRDA mode ***************************/
16786#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16787 ((INSTANCE) == USART2) || \
16788 ((INSTANCE) == USART3) || \
16789 ((INSTANCE) == UART4) || \
16790 ((INSTANCE) == UART5))
16791
16792/********************* USART Instances : Smard card mode ***********************/
16793#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
16794 ((INSTANCE) == USART2) || \
16795 ((INSTANCE) == USART3))
16796
16797/******************** LPUART Instance *****************************************/
16798#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
16799
16800/****************************** IWDG Instances ********************************/
16801#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
16802
16803/****************************** WWDG Instances ********************************/
16804#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
16805
16811/******************************************************************************/
16812/* For a painless codes migration between the STM32L4xx device product */
16813/* lines, the aliases defined below are put in place to overcome the */
16814/* differences in the interrupt handlers and IRQn definitions. */
16815/* No need to update developed interrupt code when moving across */
16816/* product lines within the same STM32L4 Family */
16817/******************************************************************************/
16818
16819/* Aliases for __IRQn */
16820#define TIM6_IRQn TIM6_DAC_IRQn
16821#define ADC1_IRQn ADC1_2_IRQn
16822#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn
16823#define TIM8_IRQn TIM8_UP_IRQn
16824#define HASH_RNG_IRQn RNG_IRQn
16825#define DFSDM0_IRQn DFSDM1_FLT0_IRQn
16826#define DFSDM1_IRQn DFSDM1_FLT1_IRQn
16827#define DFSDM2_IRQn DFSDM1_FLT2_IRQn
16828#define DFSDM3_IRQn DFSDM1_FLT3_IRQn
16829
16830/* Aliases for __IRQHandler */
16831#define TIM6_IRQHandler TIM6_DAC_IRQHandler
16832#define ADC1_IRQHandler ADC1_2_IRQHandler
16833#define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
16834#define TIM8_IRQHandler TIM8_UP_IRQHandler
16835#define HASH_RNG_IRQHandler RNG_IRQHandler
16836#define DFSDM0_IRQHandler DFSDM1_FLT0_IRQHandler
16837#define DFSDM1_IRQHandler DFSDM1_FLT1_IRQHandler
16838#define DFSDM2_IRQHandler DFSDM1_FLT2_IRQHandler
16839#define DFSDM3_IRQHandler DFSDM1_FLT3_IRQHandler
16840
16841#ifdef __cplusplus
16842}
16843#endif /* __cplusplus */
16844
16845#endif /* __STM32L471xx_H */
16846
__IO
#define __IO
Definition core_armv81mml.h:277
__I
#define __I
Definition core_armv81mml.h:274
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32L4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32l471xx.h:66
TIM8_TRG_COM_IRQn
@ TIM8_TRG_COM_IRQn
Definition stm32l471xx.h:123
PendSV_IRQn
@ PendSV_IRQn
Definition stm32l471xx.h:75
EXTI2_IRQn
@ EXTI2_IRQn
Definition stm32l471xx.h:86
DMA2_Channel4_IRQn
@ DMA2_Channel4_IRQn
Definition stm32l471xx.h:137
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition stm32l471xx.h:100
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition stm32l471xx.h:81
ADC1_2_IRQn
@ ADC1_2_IRQn
Definition stm32l471xx.h:96
DMA1_Channel2_IRQn
@ DMA1_Channel2_IRQn
Definition stm32l471xx.h:90
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition stm32l471xx.h:110
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition stm32l471xx.h:111
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition stm32l471xx.h:70
SAI1_IRQn
@ SAI1_IRQn
Definition stm32l471xx.h:151
TIM4_IRQn
@ TIM4_IRQn
Definition stm32l471xx.h:108
TIM2_IRQn
@ TIM2_IRQn
Definition stm32l471xx.h:106
DMA1_Channel1_IRQn
@ DMA1_Channel1_IRQn
Definition stm32l471xx.h:89
DMA1_Channel3_IRQn
@ DMA1_Channel3_IRQn
Definition stm32l471xx.h:91
USART2_IRQn
@ USART2_IRQn
Definition stm32l471xx.h:116
DMA2_Channel7_IRQn
@ DMA2_Channel7_IRQn
Definition stm32l471xx.h:146
SVCall_IRQn
@ SVCall_IRQn
Definition stm32l471xx.h:73
SPI3_IRQn
@ SPI3_IRQn
Definition stm32l471xx.h:129
SPI2_IRQn
@ SPI2_IRQn
Definition stm32l471xx.h:114
TIM7_IRQn
@ TIM7_IRQn
Definition stm32l471xx.h:133
RCC_IRQn
@ RCC_IRQn
Definition stm32l471xx.h:83
ADC3_IRQn
@ ADC3_IRQn
Definition stm32l471xx.h:125
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition stm32l471xx.h:144
TIM1_TRG_COM_TIM17_IRQn
@ TIM1_TRG_COM_TIM17_IRQn
Definition stm32l471xx.h:104
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition stm32l471xx.h:132
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition stm32l471xx.h:112
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition stm32l471xx.h:148
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition stm32l471xx.h:139
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition stm32l471xx.h:124
DMA1_Channel7_IRQn
@ DMA1_Channel7_IRQn
Definition stm32l471xx.h:95
UsageFault_IRQn
@ UsageFault_IRQn
Definition stm32l471xx.h:72
SysTick_IRQn
@ SysTick_IRQn
Definition stm32l471xx.h:76
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition stm32l471xx.h:150
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition stm32l471xx.h:120
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition stm32l471xx.h:149
BusFault_IRQn
@ BusFault_IRQn
Definition stm32l471xx.h:71
DMA2_Channel6_IRQn
@ DMA2_Channel6_IRQn
Definition stm32l471xx.h:145
TIM1_BRK_TIM15_IRQn
@ TIM1_BRK_TIM15_IRQn
Definition stm32l471xx.h:102
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition stm32l471xx.h:74
RNG_IRQn
@ RNG_IRQn
Definition stm32l471xx.h:155
FLASH_IRQn
@ FLASH_IRQn
Definition stm32l471xx.h:82
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition stm32l471xx.h:153
WWDG_IRQn
@ WWDG_IRQn
Definition stm32l471xx.h:78
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition stm32l471xx.h:109
TIM3_IRQn
@ TIM3_IRQn
Definition stm32l471xx.h:107
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition stm32l471xx.h:97
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition stm32l471xx.h:127
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition stm32l471xx.h:118
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition stm32l471xx.h:101
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition stm32l471xx.h:143
FPU_IRQn
@ FPU_IRQn
Definition stm32l471xx.h:156
DMA1_Channel6_IRQn
@ DMA1_Channel6_IRQn
Definition stm32l471xx.h:94
SPI1_IRQn
@ SPI1_IRQn
Definition stm32l471xx.h:113
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition stm32l471xx.h:141
HardFault_IRQn
@ HardFault_IRQn
Definition stm32l471xx.h:69
FMC_IRQn
@ FMC_IRQn
Definition stm32l471xx.h:126
EXTI0_IRQn
@ EXTI0_IRQn
Definition stm32l471xx.h:84
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition stm32l471xx.h:98
EXTI4_IRQn
@ EXTI4_IRQn
Definition stm32l471xx.h:88
SAI2_IRQn
@ SAI2_IRQn
Definition stm32l471xx.h:152
DMA2_Channel1_IRQn
@ DMA2_Channel1_IRQn
Definition stm32l471xx.h:134
DMA1_Channel5_IRQn
@ DMA1_Channel5_IRQn
Definition stm32l471xx.h:93
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition stm32l471xx.h:80
TIM8_BRK_IRQn
@ TIM8_BRK_IRQn
Definition stm32l471xx.h:121
DMA2_Channel5_IRQn
@ DMA2_Channel5_IRQn
Definition stm32l471xx.h:138
UART5_IRQn
@ UART5_IRQn
Definition stm32l471xx.h:131
DMA2_Channel2_IRQn
@ DMA2_Channel2_IRQn
Definition stm32l471xx.h:135
TIM1_UP_TIM16_IRQn
@ TIM1_UP_TIM16_IRQn
Definition stm32l471xx.h:103
USART1_IRQn
@ USART1_IRQn
Definition stm32l471xx.h:115
COMP_IRQn
@ COMP_IRQn
Definition stm32l471xx.h:142
DMA2_Channel3_IRQn
@ DMA2_Channel3_IRQn
Definition stm32l471xx.h:136
EXTI3_IRQn
@ EXTI3_IRQn
Definition stm32l471xx.h:87
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition stm32l471xx.h:68
UART4_IRQn
@ UART4_IRQn
Definition stm32l471xx.h:130
PVD_PVM_IRQn
@ PVD_PVM_IRQn
Definition stm32l471xx.h:79
DMA1_Channel4_IRQn
@ DMA1_Channel4_IRQn
Definition stm32l471xx.h:92
EXTI1_IRQn
@ EXTI1_IRQn
Definition stm32l471xx.h:85
TIM5_IRQn
@ TIM5_IRQn
Definition stm32l471xx.h:128
TIM8_UP_IRQn
@ TIM8_UP_IRQn
Definition stm32l471xx.h:122
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition stm32l471xx.h:105
LPUART1_IRQn
@ LPUART1_IRQn
Definition stm32l471xx.h:147
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition stm32l471xx.h:99
USART3_IRQn
@ USART3_IRQn
Definition stm32l471xx.h:117
TSC_IRQn
@ TSC_IRQn
Definition stm32l471xx.h:154
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition stm32l471xx.h:119
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition stm32l471xx.h:140
ADC_Common_TypeDef
Definition stm32l471xx.h:218
ADC_Common_TypeDef::RESERVED
uint32_t RESERVED
Definition stm32l471xx.h:220
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l471xx.h:221
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition stm32l471xx.h:222
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l471xx.h:219
ADC_TypeDef
Analog to Digital Converter.
Definition stm32l471xx.h:176
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition stm32l471xx.h:203
ADC_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32l471xx.h:180
ADC_TypeDef::TR2
__IO uint32_t TR2
Definition stm32l471xx.h:186
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition stm32l471xx.h:189
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition stm32l471xx.h:205
ADC_TypeDef::DR
__IO uint32_t DR
Definition stm32l471xx.h:193
ADC_TypeDef::OFR1
__IO uint32_t OFR1
Definition stm32l471xx.h:198
ADC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l471xx.h:188
ADC_TypeDef::IER
__IO uint32_t IER
Definition stm32l471xx.h:178
ADC_TypeDef::OFR3
__IO uint32_t OFR3
Definition stm32l471xx.h:200
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition stm32l471xx.h:183
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition stm32l471xx.h:196
ADC_TypeDef::OFR2
__IO uint32_t OFR2
Definition stm32l471xx.h:199
ADC_TypeDef::TR1
__IO uint32_t TR1
Definition stm32l471xx.h:185
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition stm32l471xx.h:206
ADC_TypeDef::SQR4
__IO uint32_t SQR4
Definition stm32l471xx.h:192
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition stm32l471xx.h:191
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition stm32l471xx.h:190
ADC_TypeDef::AWD3CR
__IO uint32_t AWD3CR
Definition stm32l471xx.h:209
ADC_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l471xx.h:177
ADC_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:179
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition stm32l471xx.h:213
ADC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l471xx.h:195
ADC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l471xx.h:184
ADC_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition stm32l471xx.h:181
ADC_TypeDef::RESERVED9
uint32_t RESERVED9
Definition stm32l471xx.h:211
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition stm32l471xx.h:212
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition stm32l471xx.h:204
ADC_TypeDef::AWD2CR
__IO uint32_t AWD2CR
Definition stm32l471xx.h:208
ADC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l471xx.h:194
ADC_TypeDef::TR3
__IO uint32_t TR3
Definition stm32l471xx.h:187
ADC_TypeDef::RESERVED8
uint32_t RESERVED8
Definition stm32l471xx.h:210
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition stm32l471xx.h:182
ADC_TypeDef::OFR4
__IO uint32_t OFR4
Definition stm32l471xx.h:201
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition stm32l471xx.h:243
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition stm32l471xx.h:244
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition stm32l471xx.h:247
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition stm32l471xx.h:245
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition stm32l471xx.h:246
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition stm32l471xx.h:255
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition stm32l471xx.h:257
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition stm32l471xx.h:256
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition stm32l471xx.h:231
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition stm32l471xx.h:232
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition stm32l471xx.h:235
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition stm32l471xx.h:234
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition stm32l471xx.h:233
CAN_TypeDef
Controller Area Network.
Definition stm32l471xx.h:265
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition stm32l471xx.h:270
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition stm32l471xx.h:278
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition stm32l471xx.h:266
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition stm32l471xx.h:272
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l471xx.h:280
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition stm32l471xx.h:273
CAN_TypeDef::IER
__IO uint32_t IER
Definition stm32l471xx.h:271
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition stm32l471xx.h:268
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition stm32l471xx.h:279
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition stm32l471xx.h:281
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition stm32l471xx.h:285
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l471xx.h:284
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition stm32l471xx.h:269
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition stm32l471xx.h:267
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition stm32l471xx.h:283
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l471xx.h:282
COMP_Common_TypeDef
Definition stm32l471xx.h:301
COMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l471xx.h:302
COMP_TypeDef
Comparator.
Definition stm32l471xx.h:296
COMP_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l471xx.h:297
CRC_TypeDef
CRC calculation unit.
Definition stm32l471xx.h:310
CRC_TypeDef::DR
__IO uint32_t DR
Definition stm32l471xx.h:311
CRC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l471xx.h:316
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition stm32l471xx.h:312
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition stm32l471xx.h:314
CRC_TypeDef::POL
__IO uint32_t POL
Definition stm32l471xx.h:318
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition stm32l471xx.h:313
CRC_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:315
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition stm32l471xx.h:317
DAC_TypeDef
Digital to Analog Converter.
Definition stm32l471xx.h:326
DAC_TypeDef::SHRR
__IO uint32_t SHRR
Definition stm32l471xx.h:346
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition stm32l471xx.h:335
DAC_TypeDef::MCR
__IO uint32_t MCR
Definition stm32l471xx.h:342
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition stm32l471xx.h:333
DAC_TypeDef::SHSR2
__IO uint32_t SHSR2
Definition stm32l471xx.h:344
DAC_TypeDef::SHSR1
__IO uint32_t SHSR1
Definition stm32l471xx.h:343
DAC_TypeDef::SHHR
__IO uint32_t SHHR
Definition stm32l471xx.h:345
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition stm32l471xx.h:334
DAC_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l471xx.h:341
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition stm32l471xx.h:332
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition stm32l471xx.h:328
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition stm32l471xx.h:337
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition stm32l471xx.h:338
DAC_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:327
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition stm32l471xx.h:339
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition stm32l471xx.h:329
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition stm32l471xx.h:336
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition stm32l471xx.h:331
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition stm32l471xx.h:330
DAC_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:340
DBGMCU_TypeDef
Debug MCU.
Definition stm32l471xx.h:389
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition stm32l471xx.h:390
DBGMCU_TypeDef::APB1FZR1
__IO uint32_t APB1FZR1
Definition stm32l471xx.h:392
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition stm32l471xx.h:394
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:391
DBGMCU_TypeDef::APB1FZR2
__IO uint32_t APB1FZR2
Definition stm32l471xx.h:393
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition stm32l471xx.h:375
DFSDM_Channel_TypeDef::CHDATINR
__IO uint32_t CHDATINR
Definition stm32l471xx.h:381
DFSDM_Channel_TypeDef::CHAWSCDR
__IO uint32_t CHAWSCDR
Definition stm32l471xx.h:378
DFSDM_Channel_TypeDef::CHCFGR1
__IO uint32_t CHCFGR1
Definition stm32l471xx.h:376
DFSDM_Channel_TypeDef::CHWDATAR
__IO uint32_t CHWDATAR
Definition stm32l471xx.h:380
DFSDM_Channel_TypeDef::CHCFGR2
__IO uint32_t CHCFGR2
Definition stm32l471xx.h:377
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition stm32l471xx.h:353
DFSDM_Filter_TypeDef::FLTJDATAR
__IO uint32_t FLTJDATAR
Definition stm32l471xx.h:360
DFSDM_Filter_TypeDef::FLTAWCFR
__IO uint32_t FLTAWCFR
Definition stm32l471xx.h:365
DFSDM_Filter_TypeDef::FLTICR
__IO uint32_t FLTICR
Definition stm32l471xx.h:357
DFSDM_Filter_TypeDef::FLTRDATAR
__IO uint32_t FLTRDATAR
Definition stm32l471xx.h:361
DFSDM_Filter_TypeDef::FLTEXMAX
__IO uint32_t FLTEXMAX
Definition stm32l471xx.h:366
DFSDM_Filter_TypeDef::FLTCNVTIMR
__IO uint32_t FLTCNVTIMR
Definition stm32l471xx.h:368
DFSDM_Filter_TypeDef::FLTAWSR
__IO uint32_t FLTAWSR
Definition stm32l471xx.h:364
DFSDM_Filter_TypeDef::FLTAWHTR
__IO uint32_t FLTAWHTR
Definition stm32l471xx.h:362
DFSDM_Filter_TypeDef::FLTJCHGR
__IO uint32_t FLTJCHGR
Definition stm32l471xx.h:358
DFSDM_Filter_TypeDef::FLTCR2
__IO uint32_t FLTCR2
Definition stm32l471xx.h:355
DFSDM_Filter_TypeDef::FLTCR1
__IO uint32_t FLTCR1
Definition stm32l471xx.h:354
DFSDM_Filter_TypeDef::FLTAWLTR
__IO uint32_t FLTAWLTR
Definition stm32l471xx.h:363
DFSDM_Filter_TypeDef::FLTFCR
__IO uint32_t FLTFCR
Definition stm32l471xx.h:359
DFSDM_Filter_TypeDef::FLTEXMIN
__IO uint32_t FLTEXMIN
Definition stm32l471xx.h:367
DFSDM_Filter_TypeDef::FLTISR
__IO uint32_t FLTISR
Definition stm32l471xx.h:356
DMA_Channel_TypeDef
DMA Controller.
Definition stm32l471xx.h:403
DMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition stm32l471xx.h:406
DMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l471xx.h:404
DMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition stm32l471xx.h:405
DMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition stm32l471xx.h:407
DMA_Request_TypeDef
Definition stm32l471xx.h:417
DMA_Request_TypeDef::CSELR
__IO uint32_t CSELR
Definition stm32l471xx.h:418
DMA_TypeDef
Definition stm32l471xx.h:411
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l471xx.h:412
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition stm32l471xx.h:413
EXTI_TypeDef
External Interrupt/Event Controller.
Definition stm32l471xx.h:430
EXTI_TypeDef::RTSR2
__IO uint32_t RTSR2
Definition stm32l471xx.h:441
EXTI_TypeDef::SWIER2
__IO uint32_t SWIER2
Definition stm32l471xx.h:443
EXTI_TypeDef::SWIER1
__IO uint32_t SWIER1
Definition stm32l471xx.h:435
EXTI_TypeDef::EMR2
__IO uint32_t EMR2
Definition stm32l471xx.h:440
EXTI_TypeDef::EMR1
__IO uint32_t EMR1
Definition stm32l471xx.h:432
EXTI_TypeDef::PR1
__IO uint32_t PR1
Definition stm32l471xx.h:436
EXTI_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l471xx.h:438
EXTI_TypeDef::FTSR2
__IO uint32_t FTSR2
Definition stm32l471xx.h:442
EXTI_TypeDef::IMR2
__IO uint32_t IMR2
Definition stm32l471xx.h:439
EXTI_TypeDef::IMR1
__IO uint32_t IMR1
Definition stm32l471xx.h:431
EXTI_TypeDef::RTSR1
__IO uint32_t RTSR1
Definition stm32l471xx.h:433
EXTI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l471xx.h:437
EXTI_TypeDef::FTSR1
__IO uint32_t FTSR1
Definition stm32l471xx.h:434
EXTI_TypeDef::PR2
__IO uint32_t PR2
Definition stm32l471xx.h:444
FIREWALL_TypeDef
Firewall.
Definition stm32l471xx.h:453
FIREWALL_TypeDef::CSL
__IO uint32_t CSL
Definition stm32l471xx.h:455
FIREWALL_TypeDef::NVDSL
__IO uint32_t NVDSL
Definition stm32l471xx.h:457
FIREWALL_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l471xx.h:461
FIREWALL_TypeDef::VDSL
__IO uint32_t VDSL
Definition stm32l471xx.h:459
FIREWALL_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:462
FIREWALL_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l471xx.h:460
FIREWALL_TypeDef::NVDSSA
__IO uint32_t NVDSSA
Definition stm32l471xx.h:456
FIREWALL_TypeDef::VDSSA
__IO uint32_t VDSSA
Definition stm32l471xx.h:458
FIREWALL_TypeDef::CSSA
__IO uint32_t CSSA
Definition stm32l471xx.h:454
FLASH_TypeDef
FLASH Registers.
Definition stm32l471xx.h:471
FLASH_TypeDef::PCROP2SR
__IO uint32_t PCROP2SR
Definition stm32l471xx.h:486
FLASH_TypeDef::OPTR
__IO uint32_t OPTR
Definition stm32l471xx.h:480
FLASH_TypeDef::PCROP2ER
__IO uint32_t PCROP2ER
Definition stm32l471xx.h:487
FLASH_TypeDef::RESERVED1
__IO uint32_t RESERVED1
Definition stm32l471xx.h:479
FLASH_TypeDef::WRP1AR
__IO uint32_t WRP1AR
Definition stm32l471xx.h:483
FLASH_TypeDef::WRP2AR
__IO uint32_t WRP2AR
Definition stm32l471xx.h:488
FLASH_TypeDef::WRP1BR
__IO uint32_t WRP1BR
Definition stm32l471xx.h:484
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition stm32l471xx.h:474
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition stm32l471xx.h:472
FLASH_TypeDef::PCROP1SR
__IO uint32_t PCROP1SR
Definition stm32l471xx.h:481
FLASH_TypeDef::PCROP1ER
__IO uint32_t PCROP1ER
Definition stm32l471xx.h:482
FLASH_TypeDef::WRP2BR
__IO uint32_t WRP2BR
Definition stm32l471xx.h:489
FLASH_TypeDef::PDKEYR
__IO uint32_t PDKEYR
Definition stm32l471xx.h:473
FLASH_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:477
FLASH_TypeDef::ECCR
__IO uint32_t ECCR
Definition stm32l471xx.h:478
FLASH_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:476
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition stm32l471xx.h:475
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition stm32l471xx.h:498
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition stm32l471xx.h:507
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition stm32l471xx.h:516
FMC_Bank3_TypeDef::PCR
__IO uint32_t PCR
Definition stm32l471xx.h:517
FMC_Bank3_TypeDef::PMEM
__IO uint32_t PMEM
Definition stm32l471xx.h:519
FMC_Bank3_TypeDef::ECCR
__IO uint32_t ECCR
Definition stm32l471xx.h:522
FMC_Bank3_TypeDef::PATT
__IO uint32_t PATT
Definition stm32l471xx.h:520
FMC_Bank3_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:518
FMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition stm32l471xx.h:521
GPIO_TypeDef
General Purpose I/O.
Definition stm32l471xx.h:530
GPIO_TypeDef::BRR
__IO uint32_t BRR
Definition stm32l471xx.h:540
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition stm32l471xx.h:538
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition stm32l471xx.h:531
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition stm32l471xx.h:533
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition stm32l471xx.h:535
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition stm32l471xx.h:532
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition stm32l471xx.h:534
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition stm32l471xx.h:536
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition stm32l471xx.h:537
GPIO_TypeDef::ASCR
__IO uint32_t ASCR
Definition stm32l471xx.h:541
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition stm32l471xx.h:551
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition stm32l471xx.h:554
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l471xx.h:559
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition stm32l471xx.h:556
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition stm32l471xx.h:557
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition stm32l471xx.h:561
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l471xx.h:552
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l471xx.h:558
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition stm32l471xx.h:555
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition stm32l471xx.h:562
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition stm32l471xx.h:560
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l471xx.h:553
IWDG_TypeDef
Independent WATCHDOG.
Definition stm32l471xx.h:570
IWDG_TypeDef::KR
__IO uint32_t KR
Definition stm32l471xx.h:571
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition stm32l471xx.h:573
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition stm32l471xx.h:575
IWDG_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:574
IWDG_TypeDef::PR
__IO uint32_t PR
Definition stm32l471xx.h:572
LPTIM_TypeDef
LPTIMER.
Definition stm32l471xx.h:582
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l471xx.h:584
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition stm32l471xx.h:588
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32l471xx.h:586
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition stm32l471xx.h:590
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition stm32l471xx.h:585
LPTIM_TypeDef::OR
__IO uint32_t OR
Definition stm32l471xx.h:591
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l471xx.h:583
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:587
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition stm32l471xx.h:589
OPAMP_Common_TypeDef
Definition stm32l471xx.h:606
OPAMP_Common_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l471xx.h:607
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition stm32l471xx.h:599
OPAMP_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l471xx.h:600
OPAMP_TypeDef::LPOTR
__IO uint32_t LPOTR
Definition stm32l471xx.h:602
OPAMP_TypeDef::OTR
__IO uint32_t OTR
Definition stm32l471xx.h:601
PWR_TypeDef
Power Control.
Definition stm32l471xx.h:615
PWR_TypeDef::PUCRG
__IO uint32_t PUCRG
Definition stm32l471xx.h:636
PWR_TypeDef::PDCRD
__IO uint32_t PDCRD
Definition stm32l471xx.h:631
PWR_TypeDef::RESERVED
uint32_t RESERVED
Definition stm32l471xx.h:623
PWR_TypeDef::PDCRB
__IO uint32_t PDCRB
Definition stm32l471xx.h:627
PWR_TypeDef::PDCRA
__IO uint32_t PDCRA
Definition stm32l471xx.h:625
PWR_TypeDef::PDCRH
__IO uint32_t PDCRH
Definition stm32l471xx.h:639
PWR_TypeDef::PDCRE
__IO uint32_t PDCRE
Definition stm32l471xx.h:633
PWR_TypeDef::PUCRC
__IO uint32_t PUCRC
Definition stm32l471xx.h:628
PWR_TypeDef::SCR
__IO uint32_t SCR
Definition stm32l471xx.h:622
PWR_TypeDef::PUCRF
__IO uint32_t PUCRF
Definition stm32l471xx.h:634
PWR_TypeDef::PUCRH
__IO uint32_t PUCRH
Definition stm32l471xx.h:638
PWR_TypeDef::SR2
__IO uint32_t SR2
Definition stm32l471xx.h:621
PWR_TypeDef::PDCRC
__IO uint32_t PDCRC
Definition stm32l471xx.h:629
PWR_TypeDef::PUCRD
__IO uint32_t PUCRD
Definition stm32l471xx.h:630
PWR_TypeDef::PDCRG
__IO uint32_t PDCRG
Definition stm32l471xx.h:637
PWR_TypeDef::CR4
__IO uint32_t CR4
Definition stm32l471xx.h:619
PWR_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l471xx.h:616
PWR_TypeDef::PUCRB
__IO uint32_t PUCRB
Definition stm32l471xx.h:626
PWR_TypeDef::PUCRE
__IO uint32_t PUCRE
Definition stm32l471xx.h:632
PWR_TypeDef::PDCRF
__IO uint32_t PDCRF
Definition stm32l471xx.h:635
PWR_TypeDef::SR1
__IO uint32_t SR1
Definition stm32l471xx.h:620
PWR_TypeDef::CR3
__IO uint32_t CR3
Definition stm32l471xx.h:618
PWR_TypeDef::PUCRA
__IO uint32_t PUCRA
Definition stm32l471xx.h:624
PWR_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l471xx.h:617
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition stm32l471xx.h:648
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition stm32l471xx.h:655
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition stm32l471xx.h:657
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition stm32l471xx.h:656
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition stm32l471xx.h:652
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l471xx.h:654
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition stm32l471xx.h:653
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition stm32l471xx.h:658
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition stm32l471xx.h:659
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition stm32l471xx.h:660
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:649
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition stm32l471xx.h:661
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition stm32l471xx.h:650
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:651
RCC_TypeDef
Reset and Clock Control.
Definition stm32l471xx.h:670
RCC_TypeDef::CCIPR
__IO uint32_t CCIPR
Definition stm32l471xx.h:705
RCC_TypeDef::ICSCR
__IO uint32_t ICSCR
Definition stm32l471xx.h:672
RCC_TypeDef::APB1SMENR2
__IO uint32_t APB1SMENR2
Definition stm32l471xx.h:702
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition stm32l471xx.h:707
RCC_TypeDef::CIER
__IO uint32_t CIER
Definition stm32l471xx.h:677
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition stm32l471xx.h:689
RCC_TypeDef::APB1RSTR1
__IO uint32_t APB1RSTR1
Definition stm32l471xx.h:685
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition stm32l471xx.h:673
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition stm32l471xx.h:683
RCC_TypeDef::APB2SMENR
__IO uint32_t APB2SMENR
Definition stm32l471xx.h:703
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition stm32l471xx.h:681
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l471xx.h:688
RCC_TypeDef::RESERVED6
uint32_t RESERVED6
Definition stm32l471xx.h:704
RCC_TypeDef::CICR
__IO uint32_t CICR
Definition stm32l471xx.h:679
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition stm32l471xx.h:690
RCC_TypeDef::APB1RSTR2
__IO uint32_t APB1RSTR2
Definition stm32l471xx.h:686
RCC_TypeDef::RESERVED7
uint32_t RESERVED7
Definition stm32l471xx.h:706
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition stm32l471xx.h:682
RCC_TypeDef::APB1ENR1
__IO uint32_t APB1ENR1
Definition stm32l471xx.h:693
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l471xx.h:708
RCC_TypeDef::AHB3SMENR
__IO uint32_t AHB3SMENR
Definition stm32l471xx.h:699
RCC_TypeDef::AHB2SMENR
__IO uint32_t AHB2SMENR
Definition stm32l471xx.h:698
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition stm32l471xx.h:687
RCC_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:671
RCC_TypeDef::PLLSAI2CFGR
__IO uint32_t PLLSAI2CFGR
Definition stm32l471xx.h:676
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l471xx.h:696
RCC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l471xx.h:684
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition stm32l471xx.h:695
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition stm32l471xx.h:691
RCC_TypeDef::AHB1SMENR
__IO uint32_t AHB1SMENR
Definition stm32l471xx.h:697
RCC_TypeDef::APB1SMENR1
__IO uint32_t APB1SMENR1
Definition stm32l471xx.h:701
RCC_TypeDef::RESERVED5
uint32_t RESERVED5
Definition stm32l471xx.h:700
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition stm32l471xx.h:674
RCC_TypeDef::PLLSAI1CFGR
__IO uint32_t PLLSAI1CFGR
Definition stm32l471xx.h:675
RCC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l471xx.h:692
RCC_TypeDef::CIFR
__IO uint32_t CIFR
Definition stm32l471xx.h:678
RCC_TypeDef::APB1ENR2
__IO uint32_t APB1ENR2
Definition stm32l471xx.h:694
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition stm32l471xx.h:680
RNG_TypeDef
RNG.
Definition stm32l471xx.h:979
RNG_TypeDef::DR
__IO uint32_t DR
Definition stm32l471xx.h:982
RNG_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:980
RNG_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:981
RTC_TypeDef
Real-Time Clock.
Definition stm32l471xx.h:716
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition stm32l471xx.h:729
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition stm32l471xx.h:740
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition stm32l471xx.h:731
RTC_TypeDef::BKP20R
__IO uint32_t BKP20R
Definition stm32l471xx.h:757
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition stm32l471xx.h:743
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition stm32l471xx.h:728
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition stm32l471xx.h:754
RTC_TypeDef::BKP30R
__IO uint32_t BKP30R
Definition stm32l471xx.h:767
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition stm32l471xx.h:744
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition stm32l471xx.h:732
RTC_TypeDef::DR
__IO uint32_t DR
Definition stm32l471xx.h:718
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition stm32l471xx.h:737
RTC_TypeDef::BKP26R
__IO uint32_t BKP26R
Definition stm32l471xx.h:763
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition stm32l471xx.h:725
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition stm32l471xx.h:756
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition stm32l471xx.h:735
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition stm32l471xx.h:734
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition stm32l471xx.h:726
RTC_TypeDef::TR
__IO uint32_t TR
Definition stm32l471xx.h:717
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition stm32l471xx.h:755
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition stm32l471xx.h:746
RTC_TypeDef::BKP29R
__IO uint32_t BKP29R
Definition stm32l471xx.h:766
RTC_TypeDef::BKP24R
__IO uint32_t BKP24R
Definition stm32l471xx.h:761
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition stm32l471xx.h:750
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition stm32l471xx.h:749
RTC_TypeDef::OR
__IO uint32_t OR
Definition stm32l471xx.h:736
RTC_TypeDef::BKP31R
__IO uint32_t BKP31R
Definition stm32l471xx.h:768
RTC_TypeDef::BKP25R
__IO uint32_t BKP25R
Definition stm32l471xx.h:762
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition stm32l471xx.h:727
RTC_TypeDef::reserved
uint32_t reserved
Definition stm32l471xx.h:723
RTC_TypeDef::BKP23R
__IO uint32_t BKP23R
Definition stm32l471xx.h:760
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition stm32l471xx.h:739
RTC_TypeDef::BKP22R
__IO uint32_t BKP22R
Definition stm32l471xx.h:759
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition stm32l471xx.h:747
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition stm32l471xx.h:741
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l471xx.h:720
RTC_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:719
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition stm32l471xx.h:742
RTC_TypeDef::TAMPCR
__IO uint32_t TAMPCR
Definition stm32l471xx.h:733
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition stm32l471xx.h:730
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition stm32l471xx.h:724
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition stm32l471xx.h:745
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition stm32l471xx.h:722
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition stm32l471xx.h:751
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition stm32l471xx.h:748
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition stm32l471xx.h:721
RTC_TypeDef::BKP27R
__IO uint32_t BKP27R
Definition stm32l471xx.h:764
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition stm32l471xx.h:753
RTC_TypeDef::BKP21R
__IO uint32_t BKP21R
Definition stm32l471xx.h:758
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition stm32l471xx.h:738
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition stm32l471xx.h:752
RTC_TypeDef::BKP28R
__IO uint32_t BKP28R
Definition stm32l471xx.h:765
SAI_Block_TypeDef
Definition stm32l471xx.h:781
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition stm32l471xx.h:789
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition stm32l471xx.h:788
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l471xx.h:782
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition stm32l471xx.h:785
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition stm32l471xx.h:784
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition stm32l471xx.h:786
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:787
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l471xx.h:783
SAI_TypeDef
Serial Audio Interface.
Definition stm32l471xx.h:776
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition stm32l471xx.h:777
SDMMC_TypeDef
Secure digital input/output Interface.
Definition stm32l471xx.h:798
SDMMC_TypeDef::ARG
__IO uint32_t ARG
Definition stm32l471xx.h:801
SDMMC_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l471xx.h:813
SDMMC_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition stm32l471xx.h:808
SDMMC_TypeDef::RESP3
__I uint32_t RESP3
Definition stm32l471xx.h:806
SDMMC_TypeDef::DCOUNT
__I uint32_t DCOUNT
Definition stm32l471xx.h:811
SDMMC_TypeDef::RESP2
__I uint32_t RESP2
Definition stm32l471xx.h:805
SDMMC_TypeDef::MASK
__IO uint32_t MASK
Definition stm32l471xx.h:814
SDMMC_TypeDef::DLEN
__IO uint32_t DLEN
Definition stm32l471xx.h:809
SDMMC_TypeDef::POWER
__IO uint32_t POWER
Definition stm32l471xx.h:799
SDMMC_TypeDef::FIFO
__IO uint32_t FIFO
Definition stm32l471xx.h:818
SDMMC_TypeDef::STA
__I uint32_t STA
Definition stm32l471xx.h:812
SDMMC_TypeDef::RESP1
__I uint32_t RESP1
Definition stm32l471xx.h:804
SDMMC_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition stm32l471xx.h:810
SDMMC_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition stm32l471xx.h:800
SDMMC_TypeDef::RESPCMD
__I uint32_t RESPCMD
Definition stm32l471xx.h:803
SDMMC_TypeDef::FIFOCNT
__I uint32_t FIFOCNT
Definition stm32l471xx.h:816
SDMMC_TypeDef::RESP4
__I uint32_t RESP4
Definition stm32l471xx.h:807
SDMMC_TypeDef::CMD
__IO uint32_t CMD
Definition stm32l471xx.h:802
SPI_TypeDef
Serial Peripheral Interface.
Definition stm32l471xx.h:827
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition stm32l471xx.h:833
SPI_TypeDef::DR
__IO uint32_t DR
Definition stm32l471xx.h:831
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l471xx.h:828
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition stm32l471xx.h:834
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition stm32l471xx.h:832
SPI_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:830
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l471xx.h:829
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition stm32l471xx.h:843
SWPMI_TypeDef::RFL
__IO uint32_t RFL
Definition stm32l471xx.h:850
SWPMI_TypeDef::BRR
__IO uint32_t BRR
Definition stm32l471xx.h:845
SWPMI_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l471xx.h:848
SWPMI_TypeDef::TDR
__IO uint32_t TDR
Definition stm32l471xx.h:851
SWPMI_TypeDef::IER
__IO uint32_t IER
Definition stm32l471xx.h:849
SWPMI_TypeDef::OR
__IO uint32_t OR
Definition stm32l471xx.h:853
SWPMI_TypeDef::RDR
__IO uint32_t RDR
Definition stm32l471xx.h:852
SWPMI_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l471xx.h:847
SWPMI_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:844
SWPMI_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l471xx.h:846
SYSCFG_TypeDef
System configuration controller.
Definition stm32l471xx.h:862
SYSCFG_TypeDef::SWPR
__IO uint32_t SWPR
Definition stm32l471xx.h:868
SYSCFG_TypeDef::CFGR1
__IO uint32_t CFGR1
Definition stm32l471xx.h:864
SYSCFG_TypeDef::SKR
__IO uint32_t SKR
Definition stm32l471xx.h:869
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition stm32l471xx.h:863
SYSCFG_TypeDef::SCSR
__IO uint32_t SCSR
Definition stm32l471xx.h:866
SYSCFG_TypeDef::CFGR2
__IO uint32_t CFGR2
Definition stm32l471xx.h:867
TIM_TypeDef
TIM.
Definition stm32l471xx.h:878
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition stm32l471xx.h:882
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition stm32l471xx.h:886
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition stm32l471xx.h:887
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition stm32l471xx.h:884
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition stm32l471xx.h:894
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition stm32l471xx.h:881
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition stm32l471xx.h:901
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition stm32l471xx.h:896
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition stm32l471xx.h:902
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition stm32l471xx.h:888
TIM_TypeDef::OR2
__IO uint32_t OR2
Definition stm32l471xx.h:903
TIM_TypeDef::OR3
__IO uint32_t OR3
Definition stm32l471xx.h:904
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition stm32l471xx.h:895
TIM_TypeDef::OR1
__IO uint32_t OR1
Definition stm32l471xx.h:899
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition stm32l471xx.h:889
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition stm32l471xx.h:891
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l471xx.h:879
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition stm32l471xx.h:898
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition stm32l471xx.h:893
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition stm32l471xx.h:892
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition stm32l471xx.h:885
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition stm32l471xx.h:900
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition stm32l471xx.h:890
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition stm32l471xx.h:897
TIM_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:883
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l471xx.h:880
TSC_TypeDef
Touch Sensing Controller (TSC)
Definition stm32l471xx.h:913
TSC_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l471xx.h:916
TSC_TypeDef::IOHCR
__IO uint32_t IOHCR
Definition stm32l471xx.h:918
TSC_TypeDef::IOGCSR
__IO uint32_t IOGCSR
Definition stm32l471xx.h:926
TSC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition stm32l471xx.h:921
TSC_TypeDef::IER
__IO uint32_t IER
Definition stm32l471xx.h:915
TSC_TypeDef::IOCCR
__IO uint32_t IOCCR
Definition stm32l471xx.h:924
TSC_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l471xx.h:917
TSC_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:914
TSC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition stm32l471xx.h:925
TSC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition stm32l471xx.h:919
TSC_TypeDef::IOASCR
__IO uint32_t IOASCR
Definition stm32l471xx.h:920
TSC_TypeDef::RESERVED3
uint32_t RESERVED3
Definition stm32l471xx.h:923
TSC_TypeDef::IOSCR
__IO uint32_t IOSCR
Definition stm32l471xx.h:922
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition stm32l471xx.h:935
USART_TypeDef::BRR
__IO uint32_t BRR
Definition stm32l471xx.h:939
USART_TypeDef::ICR
__IO uint32_t ICR
Definition stm32l471xx.h:946
USART_TypeDef::GTPR
__IO uint16_t GTPR
Definition stm32l471xx.h:940
USART_TypeDef::RQR
__IO uint16_t RQR
Definition stm32l471xx.h:943
USART_TypeDef::RESERVED2
uint16_t RESERVED2
Definition stm32l471xx.h:941
USART_TypeDef::RESERVED3
uint16_t RESERVED3
Definition stm32l471xx.h:944
USART_TypeDef::RESERVED4
uint16_t RESERVED4
Definition stm32l471xx.h:948
USART_TypeDef::CR1
__IO uint32_t CR1
Definition stm32l471xx.h:936
USART_TypeDef::ISR
__IO uint32_t ISR
Definition stm32l471xx.h:945
USART_TypeDef::RESERVED5
uint16_t RESERVED5
Definition stm32l471xx.h:950
USART_TypeDef::RDR
__IO uint16_t RDR
Definition stm32l471xx.h:947
USART_TypeDef::TDR
__IO uint16_t TDR
Definition stm32l471xx.h:949
USART_TypeDef::CR3
__IO uint32_t CR3
Definition stm32l471xx.h:938
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition stm32l471xx.h:942
USART_TypeDef::CR2
__IO uint32_t CR2
Definition stm32l471xx.h:937
VREFBUF_TypeDef
VREFBUF.
Definition stm32l471xx.h:958
VREFBUF_TypeDef::CCR
__IO uint32_t CCR
Definition stm32l471xx.h:960
VREFBUF_TypeDef::CSR
__IO uint32_t CSR
Definition stm32l471xx.h:959
WWDG_TypeDef
Window WATCHDOG.
Definition stm32l471xx.h:968
WWDG_TypeDef::CR
__IO uint32_t CR
Definition stm32l471xx.h:969
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition stm32l471xx.h:970
WWDG_TypeDef::SR
__IO uint32_t SR
Definition stm32l471xx.h:971
system_stm32l4xx.h
CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
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